gpu: nvgpu: vgpu: move t19x specific code to general code

- remove vgpu_t19x.h and tegra_vgpu_t19x.h
- merge t19x specific ivc commands to the big enum
- move TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT to constants

Jira EVLR-2293

Change-Id: I34344bffa03bb69e1282b1f19382e3199f9ba105
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1636128
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2018-01-10 16:06:30 -08:00
committed by mobile promotions
parent ece3d958b3
commit 9dd3bb2e62
11 changed files with 44 additions and 112 deletions

View File

@@ -30,7 +30,7 @@ int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
struct gk20a *g = c->g;
struct vm_gk20a *vm = c->vm;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt;
struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt;
/*
* Add ro map for complete sync point shim range in vm.
@@ -97,15 +97,9 @@ int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
{
struct fifo_gk20a *f = &g->fifo;
int err;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
err = vgpu_get_attribute(vgpu_get_handle(g),
TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT,
&f->t19x.max_subctx_count);
if (err) {
nvgpu_err(g, "get max_subctx_count failed %d", err);
return err;
}
f->t19x.max_subctx_count = priv->constants.max_subctx_count;
return 0;
}

View File

@@ -25,7 +25,6 @@
#include "common/linux/vgpu/dbg_vgpu.h"
#include "common/linux/vgpu/fecs_trace_vgpu.h"
#include "common/linux/vgpu/css_vgpu.h"
#include "common/linux/vgpu/vgpu_t19x.h"
#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
#include "common/linux/vgpu/gp10b/vgpu_mm_gp10b.h"
#include "common/linux/vgpu/gp10b/vgpu_gr_gp10b.h"

View File

@@ -24,7 +24,7 @@ int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_alloc_ctx_header_params *p =
&msg.params.t19x.alloc_ctx_header;
&msg.params.alloc_ctx_header;
int err;
msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
@@ -55,7 +55,7 @@ void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_free_ctx_header_params *p =
&msg.params.t19x.free_ctx_header;
&msg.params.free_ctx_header;
int err;
if (ctx->mem.gpu_va) {

View File

@@ -25,7 +25,7 @@ int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_tsg_bind_channel_ex_params *p =
&msg.params.t19x.tsg_bind_channel_ex;
&msg.params.tsg_bind_channel_ex;
int err;
gk20a_dbg_fn("");