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gpu: nvgpu: vgpu: move t19x specific code to general code

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- remove vgpu_t19x.h and tegra_vgpu_t19x.h
- merge t19x specific ivc commands to the big enum
- move TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT to constants

Jira EVLR-2293

Change-Id: I34344bffa03bb69e1282b1f19382e3199f9ba105
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1636128
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2018-01-10 16:06:30 -08:00
committed by mobile promotions
parent ece3d958b3
commit 9dd3bb2e62
11 changed files with 44 additions and 112 deletions
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7
drivers/gpu/nvgpu/common/linux/module.c
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@@ -52,9 +52,6 @@
#include "sim.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "nvgpu_gpuid_t19x.h"
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
#include "vgpu/vgpu_t19x.h"
#endif
#endif
#include "os_linux.h"
@@ -389,8 +386,8 @@ static struct of_device_id tegra_gk20a_of_match[] = {
{ .compatible = TEGRA_19x_GPU_COMPAT_TEGRA,
.data = &t19x_gpu_tegra_platform },
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
{ .compatible = TEGRA_19x_VGPU_COMPAT_TEGRA,
.data = &t19x_vgpu_tegra_platform },
{ .compatible = "nvidia,gv11b-vgpu",
.data = &gv11b_vgpu_tegra_platform},
#endif
#endif
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION

1
drivers/gpu/nvgpu/common/linux/platform_gk20a.h
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@@ -252,6 +252,7 @@ extern struct gk20a_platform gm20b_tegra_platform;
extern struct gk20a_platform gp10b_tegra_platform;
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
extern struct gk20a_platform vgpu_tegra_platform;
extern struct gk20a_platform gv11b_vgpu_tegra_platform;
#endif
#endif

12
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c
View File

@@ -30,7 +30,7 @@ int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
struct gk20a *g = c->g;
struct vm_gk20a *vm = c->vm;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt;
struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt;
/*
* Add ro map for complete sync point shim range in vm.
@@ -97,15 +97,9 @@ int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g)
{
struct fifo_gk20a *f = &g->fifo;
int err;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
err = vgpu_get_attribute(vgpu_get_handle(g),
TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT,
&f->t19x.max_subctx_count);
if (err) {
nvgpu_err(g, "get max_subctx_count failed %d", err);
return err;
}
f->t19x.max_subctx_count = priv->constants.max_subctx_count;
return 0;
}

1
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -25,7 +25,6 @@
#include "common/linux/vgpu/dbg_vgpu.h"
#include "common/linux/vgpu/fecs_trace_vgpu.h"
#include "common/linux/vgpu/css_vgpu.h"
#include "common/linux/vgpu/vgpu_t19x.h"
#include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h"
#include "common/linux/vgpu/gp10b/vgpu_mm_gp10b.h"
#include "common/linux/vgpu/gp10b/vgpu_gr_gp10b.h"

4
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c
View File

@@ -24,7 +24,7 @@ int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_alloc_ctx_header_params *p =
&msg.params.t19x.alloc_ctx_header;
&msg.params.alloc_ctx_header;
int err;
msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
@@ -55,7 +55,7 @@ void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_free_ctx_header_params *p =
&msg.params.t19x.free_ctx_header;
&msg.params.free_ctx_header;
int err;
if (ctx->mem.gpu_va) {

2
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c
View File

@@ -25,7 +25,7 @@ int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_tsg_bind_channel_ex_params *p =
&msg.params.t19x.tsg_bind_channel_ex;
&msg.params.tsg_bind_channel_ex;
int err;
gk20a_dbg_fn("");

3
drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c
View File

@@ -48,7 +48,6 @@
#include "common/linux/driver_common.h"
#ifdef CONFIG_TEGRA_19x_GPU
#include "common/linux/vgpu/vgpu_t19x.h"
#include <nvgpu_gpuid_t19x.h>
#endif
@@ -439,7 +438,7 @@ static int vgpu_init_hal(struct gk20a *g)
break;
#ifdef CONFIG_TEGRA_19x_GPU
case TEGRA_19x_GPUID:
err = vgpu_t19x_init_hal(g);
err = vgpu_gv11b_init_hal(g);
break;
#endif
default:

1
drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h
View File

@@ -103,6 +103,7 @@ int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
size_t size_out);
int vgpu_gp10b_init_hal(struct gk20a *g);
int vgpu_gv11b_init_hal(struct gk20a *g);
int vgpu_init_gpu_characteristics(struct gk20a *g);

30
drivers/gpu/nvgpu/common/linux/vgpu/vgpu_t19x.h
View File

@@ -1,30 +0,0 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _VGPU_T19X_H_
#define _VGPU_T19X_H_
struct gk20a;
int vgpu_gv11b_init_hal(struct gk20a *g);
#define vgpu_t19x_init_hal(g) vgpu_gv11b_init_hal(g)
#define TEGRA_19x_VGPU_COMPAT_TEGRA "nvidia,gv11b-vgpu"
extern struct gk20a_platform gv11b_vgpu_tegra_platform;
#define t19x_vgpu_tegra_platform gv11b_vgpu_tegra_platform
#endif

40
include/linux/tegra_vgpu.h
View File

@@ -21,10 +21,6 @@
#include <nvgpu/types.h>
#ifdef CONFIG_TEGRA_19x_GPU
#include <linux/tegra_vgpu_t19x.h>
#endif
enum {
TEGRA_VGPU_MODULE_GPU = 0,
};
@@ -112,6 +108,10 @@ enum {
TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74,
TEGRA_VGPU_CMD_TSG_RELEASE = 75,
TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76,
TEGRA_VGPU_CMD_ALLOC_CTX_HEADER = 77,
TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78,
TEGRA_VGPU_CMD_MAP_SYNCPT = 79,
TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80,
};
struct tegra_vgpu_connect_params {
@@ -484,6 +484,7 @@ struct tegra_vgpu_constants_params {
struct tegra_vgpu_engines_info engines_info;
u32 num_pce;
u32 sm_per_tpc;
u32 max_subctx_count;
};
struct tegra_vgpu_channel_cyclestats_snapshot_params {
@@ -543,6 +544,30 @@ struct tegra_vgpu_vsms_mapping_entry {
u32 global_tpc_index;
};
struct tegra_vgpu_alloc_ctx_header_params {
u64 ch_handle;
u64 ctx_header_va;
};
struct tegra_vgpu_free_ctx_header_params {
u64 ch_handle;
};
struct tegra_vgpu_map_syncpt_params {
u64 as_handle;
u64 gpu_va;
u64 len;
u64 offset;
u8 prot;
};
struct tegra_vgpu_tsg_bind_channel_ex_params {
u32 tsg_id;
u64 ch_handle;
u32 subctx_id;
u32 runqueue_sel;
};
struct tegra_vgpu_cmd_msg {
u32 cmd;
int ret;
@@ -598,9 +623,10 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper;
struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table;
struct tegra_vgpu_vsms_mapping_params vsms_mapping;
#ifdef CONFIG_TEGRA_19x_GPU
union tegra_vgpu_t19x_params t19x;
#endif
struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header;
struct tegra_vgpu_free_ctx_header_params free_ctx_header;
struct tegra_vgpu_map_syncpt_params map_syncpt;
struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex;
char padding[192];
} params;
};

55
include/linux/tegra_vgpu_t19x.h
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@@ -1,55 +0,0 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __TEGRA_VGPU_T19X_H
#define __TEGRA_VGPU_T19X_H
#define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100
#define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101
#define TEGRA_VGPU_CMD_MAP_SYNCPT 102
#define TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX 103
struct tegra_vgpu_alloc_ctx_header_params {
u64 ch_handle;
u64 ctx_header_va;
};
struct tegra_vgpu_free_ctx_header_params {
u64 ch_handle;
};
struct tegra_vgpu_map_syncpt_params {
u64 as_handle;
u64 gpu_va;
u64 len;
u64 offset;
u8 prot;
};
struct tegra_vgpu_tsg_bind_channel_ex_params {
u32 tsg_id;
u64 ch_handle;
u32 subctx_id;
u32 runqueue_sel;
};
union tegra_vgpu_t19x_params {
struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header;
struct tegra_vgpu_free_ctx_header_params free_ctx_header;
struct tegra_vgpu_map_syncpt_params map_syncpt;
struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex;
};
#define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100
#endif