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gpu: nvgpu: Remove unconditional device_info print

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Unconditional nvgpu_info() seems unnecessary for the debug prints
from device_info table parsing code. Replace them with nvgpu_log_info
prints.

Bug 2461826

Change-Id: I0f84b9a1a2eb79999575f21a85ed0b4fe84806fa
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987350
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2019-01-04 09:35:31 +05:30
committed by mobile promotions
parent 93a05937f0
commit 9dde3548fd
4 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
View File

@@ -2107,7 +2107,7 @@ int gv100_nvlink_discover_ioctrl(struct gk20a *g)
if (g->ops.top.get_num_engine_type_entries) {
ioctrl_num_entries = g->ops.top.get_num_engine_type_entries(g,
NVGPU_ENGINE_IOCTRL);
nvgpu_info(g, "ioctrl_num_entries: %d", ioctrl_num_entries);
nvgpu_log_info(g, "ioctrl_num_entries: %d", ioctrl_num_entries);
}
if (ioctrl_num_entries == 0) {

4
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Graphics FIFO (gr host)
*
* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -4291,7 +4291,7 @@ bool gk20a_fifo_find_pbdma_for_runlist(struct fifo_gk20a *f, u32 runlist_id,
runlist_bit = BIT32(runlist_id);
for (id = 0; id < f->num_pbdma; id++) {
if ((f->pbdma_map[id] & runlist_bit) != 0U) {
nvgpu_info(g, "gr info: pbdma_map[%d]=%d", id,
nvgpu_log_info(g, "gr info: pbdma_map[%d]=%d", id,
f->pbdma_map[id]);
found_pbdma_for_runlist = true;
break;

8
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B Fifo
*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -287,7 +287,7 @@ int gm20b_fifo_init_engine_info(struct fifo_gk20a *f)
/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
f->active_engines_list[f->num_engines] = dev_info.engine_id;
++f->num_engines;
nvgpu_info(g, "gr info: engine_id %d runlist_id %d intr_id %d "
nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d intr_id %d "
"reset_id %d engine_type %d engine_enum %d inst_id %d",
dev_info.engine_id,
dev_info.runlist_id,
@@ -314,7 +314,7 @@ int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
bool found_pbdma_for_runlist = false;
gr_runlist_id = gk20a_fifo_get_gr_runlist_id(g);
nvgpu_info(g, "gr_runlist_id: %d", gr_runlist_id);
nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
if (g->ops.top.get_device_info != NULL) {
for (i = NVGPU_ENGINE_COPY0; i <= NVGPU_ENGINE_COPY2; i++) {
@@ -377,7 +377,7 @@ int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
f->active_engines_list[f->num_engines] =
dev_info.engine_id;
++f->num_engines;
nvgpu_info(g, "gr info: engine_id %d runlist_id %d "
nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
"intr_id %d reset_id %d engine_type %d "
"engine_enum %d inst_id %d",
dev_info.engine_id,

8
drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B fifo
*
* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -200,12 +200,12 @@ int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
u32 lce_num_entries = 0;
gr_runlist_id = gk20a_fifo_get_gr_runlist_id(g);
nvgpu_info(g, "gr_runlist_id: %d", gr_runlist_id);
nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
if (g->ops.top.get_num_engine_type_entries != NULL) {
lce_num_entries = g->ops.top.get_num_engine_type_entries(g,
NVGPU_ENGINE_LCE);
nvgpu_info(g, "lce_num_entries: %d", lce_num_entries);
nvgpu_log_info(g, "lce_num_entries: %d", lce_num_entries);
}
for (i = 0; i < lce_num_entries; i++) {
@@ -266,7 +266,7 @@ int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
f->active_engines_list[f->num_engines] =
dev_info.engine_id;
++f->num_engines;
nvgpu_info(g, "gr info: engine_id %d runlist_id %d "
nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
"intr_id %d reset_id %d engine_type %d "
"engine_enum %d inst_id %d",
dev_info.engine_id,