From 9de30e1f95d7a5c21b7286a4344a7b4faa4ea3f0 Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Tue, 4 Sep 2018 11:24:43 +0530 Subject: [PATCH] gpu: nvgpu: boardobj: fix MISRA 10.4 Violations MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: I1e8659ee6759b05dec93bef83928bae77a9ee01b Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1812198 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/boardobj/boardobj.c | 2 +- drivers/gpu/nvgpu/boardobj/boardobjgrp.c | 18 +++++++++--------- drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c | 16 ++++++++-------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/nvgpu/boardobj/boardobj.c b/drivers/gpu/nvgpu/boardobj/boardobj.c index 2044b5b52..69a6a4426 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobj.c +++ b/drivers/gpu/nvgpu/boardobj/boardobj.c @@ -83,7 +83,7 @@ bool boardobj_implements_super(struct gk20a *g, struct boardobj *pboardobj, { nvgpu_log_info(g, " "); - return (0 != (pboardobj->type_mask & BIT(type))); + return (0U != (pboardobj->type_mask & BIT(type))); } int boardobj_pmudatainit_super(struct gk20a *g, struct boardobj *pboardobj, diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c index 683207030..20d8b0491 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.c @@ -493,8 +493,8 @@ int boardobjgrp_pmuset_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp) return -EINVAL; } - if ((pcmd->hdrsize == 0) || - (pcmd->entrysize == 0) || + if ((pcmd->hdrsize == 0U) || + (pcmd->entrysize == 0U) || (pcmd->buf == NULL)) { return -EINVAL; } @@ -518,7 +518,7 @@ int boardobjgrp_pmuset_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp) * alloc mem in vidmem & copy constructed pmu boardobjgrp data from * sysmem to vidmem */ - if (pcmd->surf.vidmem_desc.size == 0) { + if (pcmd->surf.vidmem_desc.size == 0U) { nvgpu_pmu_vidmem_surface_alloc(g, &pcmd->surf.vidmem_desc, pcmd->fbsize); } @@ -615,8 +615,8 @@ boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp, return -EINVAL; } - if ((pcmd->hdrsize == 0) || - (pcmd->entrysize == 0) || + if ((pcmd->hdrsize == 0U) || + (pcmd->entrysize == 0U) || (pcmd->buf == NULL)) { return -EINVAL; } @@ -633,7 +633,7 @@ boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp, * alloc mem in vidmem & copy constructed pmu boardobjgrp data from * sysmem to vidmem */ - if (pcmd->surf.vidmem_desc.size == 0) { + if (pcmd->surf.vidmem_desc.size == 0U) { nvgpu_pmu_vidmem_surface_alloc(g, &pcmd->surf.vidmem_desc, pcmd->fbsize); } @@ -801,7 +801,7 @@ static struct boardobj *boardobjgrp_objgetnext_final( /* Search from next element unless first object was requested */ index = (*currentindex != CTRL_BOARDOBJ_IDX_INVALID) ? - (*currentindex + 1) : 0; + (*currentindex + 1U) : 0U; /* For the cases below in which we have to return NULL */ *currentindex = CTRL_BOARDOBJ_IDX_INVALID; @@ -920,7 +920,7 @@ static void boardobjgrp_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, return; } - if (msg->msg.boardobj.grp_set.flcn_status != 0) { + if (msg->msg.boardobj.grp_set.flcn_status != 0U) { nvgpu_err(g, "cmd abort for unit %x class %x cmd id %x status %x", msg->hdr.unit_id, pboardobjgrp->pmu.classid, @@ -1001,7 +1001,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g, pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), &handlerparams.success, 1); - if (handlerparams.success == 0) { + if (handlerparams.success == 0U) { nvgpu_err(g, "could not process cmd"); status = -ETIMEDOUT; goto boardobjgrp_pmucmdsend_exit; diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c b/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c index a1dcd6d73..f37ced54b 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrpmask.c @@ -28,7 +28,7 @@ * Assures that unused bits (size .. (maskDataCount * 32 - 1)) are always zero. */ #define BOARDOBJGRPMASK_NORMALIZE(_pmask) \ - ((_pmask)->data[(_pmask)->maskdatacount-1] &= (_pmask)->lastmaskfilter) + ((_pmask)->data[(_pmask)->maskdatacount-1U] &= (_pmask)->lastmaskfilter) u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, struct ctrl_boardobjgrp_mask *extmask) @@ -43,11 +43,11 @@ u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize, mask->bitcount = bitsize; mask->maskdatacount = CTRL_BOARDOBJGRP_MASK_DATA_SIZE(bitsize); - mask->lastmaskfilter = bitsize % + mask->lastmaskfilter = U32(bitsize) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE; - mask->lastmaskfilter = (mask->lastmaskfilter == 0) ? - 0xFFFFFFFF : (u32)(BIT(mask->lastmaskfilter) - 1); + mask->lastmaskfilter = (mask->lastmaskfilter == 0U) ? + 0xFFFFFFFFU : (BIT32(mask->lastmaskfilter) - 1U); return (extmask == NULL) ? boardobjgrpmask_clr(mask) : @@ -150,7 +150,7 @@ bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask) return true; } for (index = 0; index < mask->maskdatacount; index++) { - if (mask->data[index] != 0) { + if (mask->data[index] != 0U) { return false; } } @@ -188,7 +188,7 @@ u8 boardobjgrpmask_bitidxlowest(struct boardobjgrpmask *mask) for (index = 0; index < mask->maskdatacount; index++) { u32 m = mask->data[index]; - if (m != 0) { + if (m != 0U) { LOWESTBITIDX_32(m); result = (u8)m + index * CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE; @@ -211,7 +211,7 @@ u8 boardobjgrpmask_bitidxhighest(struct boardobjgrpmask *mask) for (index = 0; index < mask->maskdatacount; index++) { u32 m = mask->data[index]; - if (m != 0) { + if (m != 0U) { HIGHESTBITIDX_32(m); result = (u8)m + index * CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE; @@ -297,7 +297,7 @@ bool boardobjgrpmask_bitget(struct boardobjgrpmask *mask, u8 bitidx) index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx); offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx); - return (mask->data[index] & BIT(offset)) != 0; + return (mask->data[index] & BIT(offset)) != 0U; } u32 boardobjgrpmask_and(struct boardobjgrpmask *dst,