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nvgpu: gpu: update runlist in vserver

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On QNX, Setting runlist is not happening till runlist submit. On Linux,
Setting runlist is happening at the time of channel open. due to
implimentations, which effect's channel configuration.

We need runlist for channel configuration from now.

Adding runlist parameter for below calls
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX

Bug 200701789

Change-Id: Ibd3262b43e38f54c76c4ae67ce683eccf4460cdc
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485256
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kadamati
2021-02-16 17:02:11 +05:30
committed by mobile promotions
parent e5491327fa
commit 9e13fd900d
2 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/vgpu/fifo/tsg_vgpu.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/channel.h> #include <nvgpu/channel.h>
#include <nvgpu/runlist.h>
#include <nvgpu/tsg.h> #include <nvgpu/tsg.h>
#include <nvgpu/bug.h> #include <nvgpu/bug.h>
@@ -105,6 +106,7 @@ int vgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch)
msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL; msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL;
p->tsg_id = tsg->tsgid; p->tsg_id = tsg->tsgid;
p->ch_handle = ch->virt_ctx; p->ch_handle = ch->virt_ctx;
p->runlist_id = ch->runlist->id;
} else { } else {
struct tegra_vgpu_tsg_bind_channel_ex_params *p = struct tegra_vgpu_tsg_bind_channel_ex_params *p =
&msg.params.tsg_bind_channel_ex; &msg.params.tsg_bind_channel_ex;
@@ -112,6 +114,7 @@ int vgpu_tsg_bind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch)
msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX; msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX;
p->tsg_id = tsg->tsgid; p->tsg_id = tsg->tsgid;
p->ch_handle = ch->virt_ctx; p->ch_handle = ch->virt_ctx;
p->runlist_id = ch->runlist->id;
p->subctx_id = ch->subctx_id; p->subctx_id = ch->subctx_id;
p->runqueue_sel = ch->runqueue_sel; p->runqueue_sel = ch->runqueue_sel;
} }

4
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -1,7 +1,7 @@
/* /*
* Tegra GPU Virtualization Interfaces to Server * Tegra GPU Virtualization Interfaces to Server
* *
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -407,6 +407,7 @@ struct tegra_vgpu_gr_ctx_params {
struct tegra_vgpu_tsg_bind_unbind_channel_params { struct tegra_vgpu_tsg_bind_unbind_channel_params {
u32 tsg_id; u32 tsg_id;
u64 ch_handle; u64 ch_handle;
u32 runlist_id;
}; };
struct tegra_vgpu_tsg_preempt_params { struct tegra_vgpu_tsg_preempt_params {
@@ -632,6 +633,7 @@ struct tegra_vgpu_map_syncpt_params {
struct tegra_vgpu_tsg_bind_channel_ex_params { struct tegra_vgpu_tsg_bind_channel_ex_params {
u32 tsg_id; u32 tsg_id;
u64 ch_handle; u64 ch_handle;
u32 runlist_id;
u32 subctx_id; u32 subctx_id;
u32 runqueue_sel; u32 runqueue_sel;
}; };