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gpu: nvgpu: add struct nvgpu_sched_ctrl to gk20a

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Add struct nvgpu_sched_ctrl to struct gk20a
Delete struct gk20a_sched_ctrl from struct nvgpu_os_linux
Update sched_ctrl functions to use the nvgpu_sched_ctrl struct

Bug 200576520

Change-Id: I35b13219e5ef0a8a03333dfd7d46e1d308aec541
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279152
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Satish Arora <satisha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Peter Daifuku
2020-01-14 11:14:38 -08:00
committed by mobile promotions
parent eb429023cf
commit 9e9046f03c
7 changed files with 99 additions and 91 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* *
* GK20A Graphics * GK20A Graphics
* *
@@ -71,6 +71,7 @@ struct nvgpu_setup_bind_args;
#include <nvgpu/ecc.h> #include <nvgpu/ecc.h>
#include <nvgpu/tsg.h> #include <nvgpu/tsg.h>
#include <nvgpu/sec2.h> #include <nvgpu/sec2.h>
#include <nvgpu/sched.h>
#include "gk20a/clk_gk20a.h" #include "gk20a/clk_gk20a.h"
#include "gk20a/ce2_gk20a.h" #include "gk20a/ce2_gk20a.h"
@@ -1478,6 +1479,7 @@ struct gk20a {
struct pmgr_pmupstate pmgr_pmu; struct pmgr_pmupstate pmgr_pmu;
struct therm_pmupstate therm_pmu; struct therm_pmupstate therm_pmu;
struct nvgpu_sec2 sec2; struct nvgpu_sec2 sec2;
struct nvgpu_sched_ctrl sched_ctrl;
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
struct railgate_stats pstats; struct railgate_stats pstats;

42
drivers/gpu/nvgpu/include/nvgpu/sched.h Normal file
View File

@@ -0,0 +1,42 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NVGPU_SCHED_COMMON_H
#define __NVGPU_SCHED_COMMON_H
struct nvgpu_sched_ctrl {
struct nvgpu_mutex control_lock;
bool control_locked;
bool sw_ready;
struct nvgpu_mutex status_lock;
struct nvgpu_mutex busy_lock;
u64 status;
size_t bitmap_size;
u64 *active_tsg_bitmap;
u64 *recent_tsg_bitmap;
u64 *ref_tsg_bitmap;
struct nvgpu_cond readout_wq;
};
#endif /* __NVGPU_SCHED_COMMON_H */

5
drivers/gpu/nvgpu/os/linux/debug_sched.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 NVIDIA Corporation. All rights reserved. * Copyright (C) 2017-2020 NVIDIA Corporation. All rights reserved.
* *
* This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and
@@ -21,8 +21,7 @@
static int gk20a_sched_debugfs_show(struct seq_file *s, void *unused) static int gk20a_sched_debugfs_show(struct seq_file *s, void *unused)
{ {
struct gk20a *g = s->private; struct gk20a *g = s->private;
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
bool sched_busy = true; bool sched_busy = true;
int n = sched->bitmap_size / sizeof(u64); int n = sched->bitmap_size / sizeof(u64);

11
drivers/gpu/nvgpu/os/linux/ioctl_tsg.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -58,8 +58,7 @@ static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g, static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
struct channel_gk20a *ch; struct channel_gk20a *ch;
struct gr_gk20a *gr = &g->gr; struct gr_gk20a *gr = &g->gr;
int err = 0; int err = 0;
@@ -484,8 +483,7 @@ int nvgpu_ioctl_tsg_dev_release(struct inode *inode, struct file *filp)
static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g, static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg) struct tsg_gk20a *tsg, struct nvgpu_runlist_interleave_args *arg)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
u32 level = arg->level; u32 level = arg->level;
int err; int err;
@@ -514,8 +512,7 @@ done:
static int gk20a_tsg_ioctl_set_timeslice(struct gk20a *g, static int gk20a_tsg_ioctl_set_timeslice(struct gk20a *g,
struct tsg_gk20a *tsg, struct nvgpu_timeslice_args *arg) struct tsg_gk20a *tsg, struct nvgpu_timeslice_args *arg)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
int err; int err;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);

4
drivers/gpu/nvgpu/os/linux/os_linux.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -167,8 +167,6 @@ struct nvgpu_os_linux {
struct rw_semaphore busy_lock; struct rw_semaphore busy_lock;
struct gk20a_sched_ctrl sched_ctrl;
bool init_done; bool init_done;
}; };

103
drivers/gpu/nvgpu/os/linux/sched.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -36,8 +36,8 @@
ssize_t gk20a_sched_dev_read(struct file *filp, char __user *buf, ssize_t gk20a_sched_dev_read(struct file *filp, char __user *buf,
size_t size, loff_t *off) size_t size, loff_t *off)
{ {
struct gk20a_sched_ctrl *sched = filp->private_data; struct gk20a *g = filp->private_data;
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct nvgpu_sched_event_arg event = { 0 }; struct nvgpu_sched_event_arg event = { 0 };
int err; int err;
@@ -77,8 +77,8 @@ ssize_t gk20a_sched_dev_read(struct file *filp, char __user *buf,
unsigned int gk20a_sched_dev_poll(struct file *filp, poll_table *wait) unsigned int gk20a_sched_dev_poll(struct file *filp, poll_table *wait)
{ {
struct gk20a_sched_ctrl *sched = filp->private_data; struct gk20a *g = filp->private_data;
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
unsigned int mask = 0; unsigned int mask = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
@@ -92,10 +92,10 @@ unsigned int gk20a_sched_dev_poll(struct file *filp, poll_table *wait)
return mask; return mask;
} }
static int gk20a_sched_dev_ioctl_get_tsgs(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_get_tsgs(struct gk20a *g,
struct nvgpu_sched_get_tsgs_args *arg) struct nvgpu_sched_get_tsgs_args *arg)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx", nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx",
arg->size, arg->buffer); arg->size, arg->buffer);
@@ -116,10 +116,10 @@ static int gk20a_sched_dev_ioctl_get_tsgs(struct gk20a_sched_ctrl *sched,
return 0; return 0;
} }
static int gk20a_sched_dev_ioctl_get_recent_tsgs(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_get_recent_tsgs(struct gk20a *g,
struct nvgpu_sched_get_tsgs_args *arg) struct nvgpu_sched_get_tsgs_args *arg)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx", nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "size=%u buffer=%llx",
arg->size, arg->buffer); arg->size, arg->buffer);
@@ -142,10 +142,10 @@ static int gk20a_sched_dev_ioctl_get_recent_tsgs(struct gk20a_sched_ctrl *sched,
return 0; return 0;
} }
static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a *g,
struct nvgpu_sched_get_tsgs_by_pid_args *arg) struct nvgpu_sched_get_tsgs_by_pid_args *arg)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
u64 *bitmap; u64 *bitmap;
@@ -162,7 +162,7 @@ static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a_sched_ctrl *sched,
return -ENOSPC; return -ENOSPC;
} }
bitmap = nvgpu_kzalloc(sched->g, sched->bitmap_size); bitmap = nvgpu_kzalloc(g, sched->bitmap_size);
if (!bitmap) if (!bitmap)
return -ENOMEM; return -ENOMEM;
@@ -180,15 +180,14 @@ static int gk20a_sched_dev_ioctl_get_tsgs_by_pid(struct gk20a_sched_ctrl *sched,
bitmap, sched->bitmap_size)) bitmap, sched->bitmap_size))
err = -EFAULT; err = -EFAULT;
nvgpu_kfree(sched->g, bitmap); nvgpu_kfree(g, bitmap);
return err; return err;
} }
static int gk20a_sched_dev_ioctl_get_params(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_get_params(struct gk20a *g,
struct nvgpu_sched_tsg_get_params_args *arg) struct nvgpu_sched_tsg_get_params_args *arg)
{ {
struct gk20a *g = sched->g;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
u32 tsgid = arg->tsgid; u32 tsgid = arg->tsgid;
@@ -219,10 +218,9 @@ static int gk20a_sched_dev_ioctl_get_params(struct gk20a_sched_ctrl *sched,
} }
static int gk20a_sched_dev_ioctl_tsg_set_timeslice( static int gk20a_sched_dev_ioctl_tsg_set_timeslice(
struct gk20a_sched_ctrl *sched, struct gk20a *g,
struct nvgpu_sched_tsg_timeslice_args *arg) struct nvgpu_sched_tsg_timeslice_args *arg)
{ {
struct gk20a *g = sched->g;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
u32 tsgid = arg->tsgid; u32 tsgid = arg->tsgid;
@@ -254,10 +252,9 @@ done:
} }
static int gk20a_sched_dev_ioctl_tsg_set_runlist_interleave( static int gk20a_sched_dev_ioctl_tsg_set_runlist_interleave(
struct gk20a_sched_ctrl *sched, struct gk20a *g,
struct nvgpu_sched_tsg_runlist_interleave_args *arg) struct nvgpu_sched_tsg_runlist_interleave_args *arg)
{ {
struct gk20a *g = sched->g;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
u32 tsgid = arg->tsgid; u32 tsgid = arg->tsgid;
@@ -288,9 +285,9 @@ done:
return err; return err;
} }
static int gk20a_sched_dev_ioctl_lock_control(struct gk20a_sched_ctrl *sched) static int gk20a_sched_dev_ioctl_lock_control(struct gk20a *g)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
@@ -300,9 +297,9 @@ static int gk20a_sched_dev_ioctl_lock_control(struct gk20a_sched_ctrl *sched)
return 0; return 0;
} }
static int gk20a_sched_dev_ioctl_unlock_control(struct gk20a_sched_ctrl *sched) static int gk20a_sched_dev_ioctl_unlock_control(struct gk20a *g)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
@@ -312,21 +309,19 @@ static int gk20a_sched_dev_ioctl_unlock_control(struct gk20a_sched_ctrl *sched)
return 0; return 0;
} }
static int gk20a_sched_dev_ioctl_get_api_version(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_get_api_version(struct gk20a *g,
struct nvgpu_sched_api_version_args *args) struct nvgpu_sched_api_version_args *args)
{ {
struct gk20a *g = sched->g;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " "); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, " ");
args->version = NVGPU_SCHED_API_VERSION; args->version = NVGPU_SCHED_API_VERSION;
return 0; return 0;
} }
static int gk20a_sched_dev_ioctl_get_tsg(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_get_tsg(struct gk20a *g,
struct nvgpu_sched_tsg_refcount_args *arg) struct nvgpu_sched_tsg_refcount_args *arg)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
u32 tsgid = arg->tsgid; u32 tsgid = arg->tsgid;
@@ -360,10 +355,10 @@ static int gk20a_sched_dev_ioctl_get_tsg(struct gk20a_sched_ctrl *sched,
return 0; return 0;
} }
static int gk20a_sched_dev_ioctl_put_tsg(struct gk20a_sched_ctrl *sched, static int gk20a_sched_dev_ioctl_put_tsg(struct gk20a *g,
struct nvgpu_sched_tsg_refcount_args *arg) struct nvgpu_sched_tsg_refcount_args *arg)
{ {
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
u32 tsgid = arg->tsgid; u32 tsgid = arg->tsgid;
@@ -395,13 +390,13 @@ int gk20a_sched_dev_open(struct inode *inode, struct file *filp)
struct nvgpu_os_linux *l = container_of(inode->i_cdev, struct nvgpu_os_linux *l = container_of(inode->i_cdev,
struct nvgpu_os_linux, sched.cdev); struct nvgpu_os_linux, sched.cdev);
struct gk20a *g; struct gk20a *g;
struct gk20a_sched_ctrl *sched; struct nvgpu_sched_ctrl *sched;
int err = 0; int err = 0;
g = gk20a_get(&l->g); g = gk20a_get(&l->g);
if (!g) if (!g)
return -ENODEV; return -ENODEV;
sched = &l->sched_ctrl; sched = &g->sched_ctrl;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "g=%p", g); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "g=%p", g);
@@ -422,7 +417,7 @@ int gk20a_sched_dev_open(struct inode *inode, struct file *filp)
sched->bitmap_size); sched->bitmap_size);
memset(sched->ref_tsg_bitmap, 0, sched->bitmap_size); memset(sched->ref_tsg_bitmap, 0, sched->bitmap_size);
filp->private_data = sched; filp->private_data = g;
nvgpu_log(g, gpu_dbg_sched, "filp=%p sched=%p", filp, sched); nvgpu_log(g, gpu_dbg_sched, "filp=%p sched=%p", filp, sched);
free_ref: free_ref:
@@ -434,8 +429,7 @@ free_ref:
long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd, long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg) unsigned long arg)
{ {
struct gk20a_sched_ctrl *sched = filp->private_data; struct gk20a *g = filp->private_data;
struct gk20a *g = sched->g;
u8 buf[NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE]; u8 buf[NVGPU_CTXSW_IOCTL_MAX_ARG_SIZE];
int err = 0; int err = 0;
@@ -455,45 +449,45 @@ long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd,
switch (cmd) { switch (cmd) {
case NVGPU_SCHED_IOCTL_GET_TSGS: case NVGPU_SCHED_IOCTL_GET_TSGS:
err = gk20a_sched_dev_ioctl_get_tsgs(sched, err = gk20a_sched_dev_ioctl_get_tsgs(g,
(struct nvgpu_sched_get_tsgs_args *)buf); (struct nvgpu_sched_get_tsgs_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_GET_RECENT_TSGS: case NVGPU_SCHED_IOCTL_GET_RECENT_TSGS:
err = gk20a_sched_dev_ioctl_get_recent_tsgs(sched, err = gk20a_sched_dev_ioctl_get_recent_tsgs(g,
(struct nvgpu_sched_get_tsgs_args *)buf); (struct nvgpu_sched_get_tsgs_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_GET_TSGS_BY_PID: case NVGPU_SCHED_IOCTL_GET_TSGS_BY_PID:
err = gk20a_sched_dev_ioctl_get_tsgs_by_pid(sched, err = gk20a_sched_dev_ioctl_get_tsgs_by_pid(g,
(struct nvgpu_sched_get_tsgs_by_pid_args *)buf); (struct nvgpu_sched_get_tsgs_by_pid_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_TSG_GET_PARAMS: case NVGPU_SCHED_IOCTL_TSG_GET_PARAMS:
err = gk20a_sched_dev_ioctl_get_params(sched, err = gk20a_sched_dev_ioctl_get_params(g,
(struct nvgpu_sched_tsg_get_params_args *)buf); (struct nvgpu_sched_tsg_get_params_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE: case NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE:
err = gk20a_sched_dev_ioctl_tsg_set_timeslice(sched, err = gk20a_sched_dev_ioctl_tsg_set_timeslice(g,
(struct nvgpu_sched_tsg_timeslice_args *)buf); (struct nvgpu_sched_tsg_timeslice_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_TSG_SET_RUNLIST_INTERLEAVE: case NVGPU_SCHED_IOCTL_TSG_SET_RUNLIST_INTERLEAVE:
err = gk20a_sched_dev_ioctl_tsg_set_runlist_interleave(sched, err = gk20a_sched_dev_ioctl_tsg_set_runlist_interleave(g,
(struct nvgpu_sched_tsg_runlist_interleave_args *)buf); (struct nvgpu_sched_tsg_runlist_interleave_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_LOCK_CONTROL: case NVGPU_SCHED_IOCTL_LOCK_CONTROL:
err = gk20a_sched_dev_ioctl_lock_control(sched); err = gk20a_sched_dev_ioctl_lock_control(g);
break; break;
case NVGPU_SCHED_IOCTL_UNLOCK_CONTROL: case NVGPU_SCHED_IOCTL_UNLOCK_CONTROL:
err = gk20a_sched_dev_ioctl_unlock_control(sched); err = gk20a_sched_dev_ioctl_unlock_control(g);
break; break;
case NVGPU_SCHED_IOCTL_GET_API_VERSION: case NVGPU_SCHED_IOCTL_GET_API_VERSION:
err = gk20a_sched_dev_ioctl_get_api_version(sched, err = gk20a_sched_dev_ioctl_get_api_version(g,
(struct nvgpu_sched_api_version_args *)buf); (struct nvgpu_sched_api_version_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_GET_TSG: case NVGPU_SCHED_IOCTL_GET_TSG:
err = gk20a_sched_dev_ioctl_get_tsg(sched, err = gk20a_sched_dev_ioctl_get_tsg(g,
(struct nvgpu_sched_tsg_refcount_args *)buf); (struct nvgpu_sched_tsg_refcount_args *)buf);
break; break;
case NVGPU_SCHED_IOCTL_PUT_TSG: case NVGPU_SCHED_IOCTL_PUT_TSG:
err = gk20a_sched_dev_ioctl_put_tsg(sched, err = gk20a_sched_dev_ioctl_put_tsg(g,
(struct nvgpu_sched_tsg_refcount_args *)buf); (struct nvgpu_sched_tsg_refcount_args *)buf);
break; break;
default: default:
@@ -516,8 +510,8 @@ long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd,
int gk20a_sched_dev_release(struct inode *inode, struct file *filp) int gk20a_sched_dev_release(struct inode *inode, struct file *filp)
{ {
struct gk20a_sched_ctrl *sched = filp->private_data; struct gk20a *g = filp->private_data;
struct gk20a *g = sched->g; struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
unsigned int tsgid; unsigned int tsgid;
@@ -544,8 +538,7 @@ int gk20a_sched_dev_release(struct inode *inode, struct file *filp)
void gk20a_sched_ctrl_tsg_added(struct gk20a *g, struct tsg_gk20a *tsg) void gk20a_sched_ctrl_tsg_added(struct gk20a *g, struct tsg_gk20a *tsg)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
int err; int err;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -570,8 +563,7 @@ void gk20a_sched_ctrl_tsg_added(struct gk20a *g, struct tsg_gk20a *tsg)
void gk20a_sched_ctrl_tsg_removed(struct gk20a *g, struct tsg_gk20a *tsg) void gk20a_sched_ctrl_tsg_removed(struct gk20a *g, struct tsg_gk20a *tsg)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -593,15 +585,13 @@ void gk20a_sched_ctrl_tsg_removed(struct gk20a *g, struct tsg_gk20a *tsg)
int gk20a_sched_ctrl_init(struct gk20a *g) int gk20a_sched_ctrl_init(struct gk20a *g)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
int err; int err;
if (sched->sw_ready) if (sched->sw_ready)
return 0; return 0;
sched->g = g;
sched->bitmap_size = roundup(f->num_channels, 64) / 8; sched->bitmap_size = roundup(f->num_channels, 64) / 8;
sched->status = 0; sched->status = 0;
@@ -658,8 +648,7 @@ free_active:
void gk20a_sched_ctrl_cleanup(struct gk20a *g) void gk20a_sched_ctrl_cleanup(struct gk20a *g)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
nvgpu_kfree(g, sched->active_tsg_bitmap); nvgpu_kfree(g, sched->active_tsg_bitmap);
nvgpu_kfree(g, sched->recent_tsg_bitmap); nvgpu_kfree(g, sched->recent_tsg_bitmap);

21
drivers/gpu/nvgpu/os/linux/sched.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -21,25 +21,6 @@ struct gpu_ops;
struct tsg_gk20a; struct tsg_gk20a;
struct poll_table_struct; struct poll_table_struct;
struct gk20a_sched_ctrl {
struct gk20a *g;
struct nvgpu_mutex control_lock;
bool control_locked;
bool sw_ready;
struct nvgpu_mutex status_lock;
struct nvgpu_mutex busy_lock;
u64 status;
size_t bitmap_size;
u64 *active_tsg_bitmap;
u64 *recent_tsg_bitmap;
u64 *ref_tsg_bitmap;
struct nvgpu_cond readout_wq;
};
int gk20a_sched_dev_release(struct inode *inode, struct file *filp); int gk20a_sched_dev_release(struct inode *inode, struct file *filp);
int gk20a_sched_dev_open(struct inode *inode, struct file *filp); int gk20a_sched_dev_open(struct inode *inode, struct file *filp);
long gk20a_sched_dev_ioctl(struct file *, unsigned int, unsigned long); long gk20a_sched_dev_ioctl(struct file *, unsigned int, unsigned long);