gpu: nvgpu: ensure pma byte buffer address fits in 32 bits

Right now PMA byte buffer address is allocated in the range of
0x1ffc010000. The register that stores this address is only 32-bit and
there is no corresponding _hi() register, so the address must fit in
32 bits.

Update nvgpu_vm_init() parameters in nvgpu_perfbuf_init_vm() so that a
low_hole of only 4K is used. This allows the address to be allocated
in the range of 0x4000000.

Also map byte buffer before PMA stream buffer so that byte buffer always
gets lower address.

There is only one PMA stream buffer allowed to be mapped right now so
this works for now. But in future multiple buffers can be mapped and this
solution needs to be reworked.

Bug 2510974
Jira NVGPU-5360

Change-Id: Ief1a9ee54d554e3bc13c7a9567934dcbeaefbcc6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2418520
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-09-23 16:58:30 +05:30
committed by Alex Waterman
parent 1a914b3699
commit 9e94e118fe
2 changed files with 14 additions and 16 deletions

View File

@@ -363,6 +363,14 @@ static int nvgpu_prof_ioctl_alloc_pma_stream(struct nvgpu_profiler_object_priv *
return err;
}
err = nvgpu_vm_map_buffer(mm->perfbuf.vm, args->pma_bytes_available_buffer_fd,
&pma_bytes_available_buffer_offset, 0, SZ_4K, 0, 0,
0, 0, NULL);
if (err != 0) {
nvgpu_err(g, "failed to map available bytes buffer");
goto err_put_vm;
}
/*
* Size register is 32-bit in HW, ensure requested size does
* not violate that.
@@ -374,22 +382,14 @@ static int nvgpu_prof_ioctl_alloc_pma_stream(struct nvgpu_profiler_object_priv *
0, 0, NULL);
if (err != 0) {
nvgpu_err(g, "failed to map PMA buffer");
goto err_put_vm;
}
err = nvgpu_vm_map_buffer(mm->perfbuf.vm, args->pma_bytes_available_buffer_fd,
&pma_bytes_available_buffer_offset, 0, SZ_4K, 0, 0,
0, 0, NULL);
if (err != 0) {
nvgpu_err(g, "failed to map available bytes buffer");
goto err_unmap_pma;
goto err_unmap_bytes_available;
}
dmabuf = dma_buf_get(args->pma_bytes_available_buffer_fd);
if (IS_ERR(dmabuf)) {
err = -EINVAL;
nvgpu_err(g, "failed to get available bytes buffer FD");
goto err_unmap_bytes_available;
goto err_unmap_pma;
}
cpuva = dma_buf_vmap(dmabuf);
@@ -415,10 +415,10 @@ static int nvgpu_prof_ioctl_alloc_pma_stream(struct nvgpu_profiler_object_priv *
err_dma_buf_put:
dma_buf_put(dmabuf);
err_unmap_bytes_available:
nvgpu_vm_unmap(mm->perfbuf.vm, pma_bytes_available_buffer_offset, NULL);
err_unmap_pma:
nvgpu_vm_unmap(mm->perfbuf.vm, args->pma_buffer_offset, NULL);
err_unmap_bytes_available:
nvgpu_vm_unmap(mm->perfbuf.vm, pma_bytes_available_buffer_offset, NULL);
err_put_vm:
nvgpu_perfbuf_deinit_vm(g);
nvgpu_profiler_pm_resource_release(prof,