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gpu: nvgpu: Move Intr handling common code to CIC

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CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.

Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic

JIRA NVGPU-6899

Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2021-05-25 11:08:28 +00:00
committed by mobile promotions
parent 9034b1676e
commit 9f43914933
42 changed files with 726 additions and 695 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -45,6 +45,7 @@
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/device.h>
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu/engines.h>
@@ -188,10 +189,10 @@ static void disable_gr_interrupts(struct gk20a *g)
g->ops.gr.intr.enable_exceptions(g, g->gr->config, false);
/** Disable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_GR,
MC_INTR_DISABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_GR,
MC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
NVGPU_CIC_INTR_DISABLE);
}
int nvgpu_gr_suspend(struct gk20a *g)
@@ -592,8 +593,8 @@ static int gr_init_prepare_hw(struct gk20a *g)
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
/** Enable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
return nvgpu_gr_exec_with_ret_for_each_instance(g,
gr_init_prepare_hw_impl(g));
@@ -710,8 +711,8 @@ static int nvgpu_gr_enable_hw_for_instance(struct gk20a *g)
nvgpu_cg_elcg_disable_no_wait(g);
/** Enable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
err = gr_init_prepare_hw_impl(g);
if (err != 0) {