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gpu: nvgpu: Move Intr handling common code to CIC

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CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.

Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic

JIRA NVGPU-6899

Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2021-05-25 11:08:28 +00:00
committed by mobile promotions
parent 9034b1676e
commit 9f43914933
42 changed files with 726 additions and 695 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/nvgpu/os/linux/module.c
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@@ -61,6 +61,7 @@
#include <nvgpu/cyclestats_snapshot.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include "platform_gk20a.h"
#include "sysfs.h"
@@ -928,32 +929,32 @@ u64 nvgpu_resource_addr(struct platform_device *dev, int i)
static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 err = nvgpu_intr_stall_isr(g);
u32 err = nvgpu_cic_intr_stall_isr(g);
return err == NVGPU_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
return err == NVGPU_CIC_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
}
static irqreturn_t gk20a_intr_thread_isr_stall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_intr_stall_handle(g);
nvgpu_cic_intr_stall_handle(g);
return IRQ_HANDLED;
}
static irqreturn_t gk20a_intr_isr_nonstall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 err = nvgpu_intr_nonstall_isr(g);
u32 err = nvgpu_cic_intr_nonstall_isr(g);
return err == NVGPU_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
return err == NVGPU_CIC_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
}
static irqreturn_t gk20a_intr_thread_isr_nonstall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_intr_nonstall_handle(g);
nvgpu_cic_intr_nonstall_handle(g);
return IRQ_HANDLED;
}
@@ -1498,7 +1499,7 @@ int nvgpu_wait_for_gpu_idle(struct gk20a *g)
goto out;
}
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
out:
return ret;
}
@@ -1517,7 +1518,7 @@ void gk20a_driver_start_unload(struct gk20a *g)
nvgpu_wait_for_idle(g);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
}
static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a)