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gpu: nvgpu: Move Intr handling common code to CIC

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CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.

Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic

JIRA NVGPU-6899

Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2021-05-25 11:08:28 +00:00
committed by mobile promotions
parent 9034b1676e
commit 9f43914933
42 changed files with 726 additions and 695 deletions
Download Patch File Download Diff File Expand all files Collapse all files

67
userspace/units/mc/nvgpu-mc.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/hal_init.h>
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
@@ -48,27 +49,27 @@
#define ACTIVE_GR_ID 1
#define ACTIVE_CE_ID 2
#define STALL_EN_REG mc_intr_en_set_r(NVGPU_MC_INTR_STALLING)
#define STALL_DIS_REG mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING)
#define NONSTALL_EN_REG mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING)
#define NONSTALL_DIS_REG mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING)
#define STALL_PENDING_REG mc_intr_r(NVGPU_MC_INTR_STALLING)
#define NONSTALL_PENDING_REG mc_intr_r(NVGPU_MC_INTR_NONSTALLING)
#define STALL_EN_REG mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING)
#define STALL_DIS_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_EN_REG mc_intr_en_set_r(NVGPU_CIC_INTR_NONSTALLING)
#define NONSTALL_DIS_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING)
#define STALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_NONSTALLING)
struct mc_unit {
u32 num;
u32 bit;
};
static struct mc_unit mc_units[] = {
{ MC_INTR_UNIT_BUS, mc_intr_pbus_pending_f() },
{ MC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ MC_INTR_UNIT_PRIV_RING, mc_intr_priv_ring_pending_f() },
{ MC_INTR_UNIT_FIFO, mc_intr_pfifo_pending_f() },
{ MC_INTR_UNIT_LTC, mc_intr_ltc_pending_f() },
{ MC_INTR_UNIT_HUB, mc_intr_replayable_fault_pending_f() },
{ MC_INTR_UNIT_GR, (1 << ACTIVE_GR_ID) /* nvgpu_gr_engine_interrupt_mask() */},
{ MC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ MC_INTR_UNIT_CE, (1 << ACTIVE_CE_ID) /* nvgpu_ce_engine_interrupt_mask() */ },
{ NVGPU_CIC_INTR_UNIT_BUS, mc_intr_pbus_pending_f() },
{ NVGPU_CIC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ NVGPU_CIC_INTR_UNIT_PRIV_RING, mc_intr_priv_ring_pending_f() },
{ NVGPU_CIC_INTR_UNIT_FIFO, mc_intr_pfifo_pending_f() },
{ NVGPU_CIC_INTR_UNIT_LTC, mc_intr_ltc_pending_f() },
{ NVGPU_CIC_INTR_UNIT_HUB, mc_intr_replayable_fault_pending_f() },
{ NVGPU_CIC_INTR_UNIT_GR, (1 << ACTIVE_GR_ID) /* nvgpu_gr_engine_interrupt_mask() */},
{ NVGPU_CIC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ NVGPU_CIC_INTR_UNIT_CE, (1 << ACTIVE_CE_ID) /* nvgpu_ce_engine_interrupt_mask() */ },
};
#define NUM_MC_UNITS ARRAY_SIZE(mc_units)
@@ -283,7 +284,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit = mc_units[i].num;
/* enable stall intr */
nvgpu_mc_intr_stall_unit_config(g, unit, true);
nvgpu_cic_intr_stall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable stall intr for unit %u val=0x%08x\n",
@@ -291,7 +292,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_mc_intr_stall_unit_config(g, unit, false);
nvgpu_cic_intr_stall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n",
@@ -299,7 +300,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* enable nonstall intr */
nvgpu_mc_intr_nonstall_unit_config(g, unit, true);
nvgpu_cic_intr_nonstall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable nonstall intr for unit %u val=0x%08x\n",
@@ -307,7 +308,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_mc_intr_nonstall_unit_config(g, unit, false);
nvgpu_cic_intr_nonstall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n",
@@ -317,7 +318,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0); /* clear reg */
nvgpu_mc_intr_stall_unit_config(g, U32_MAX, true);
nvgpu_cic_intr_stall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -326,7 +327,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear reg */
nvgpu_mc_intr_nonstall_unit_config(g, U32_MAX, true);
nvgpu_cic_intr_nonstall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -354,18 +355,18 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
g->mc.intr_mask_restore[1] = 0U;
/* enable something to pause and resume */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PRIV_RING, true);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_BUS, true);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
/* pause stall */
nvgpu_mc_intr_stall_pause(g);
nvgpu_cic_intr_stall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause stall intr\n");
}
/* pause nonstall */
nvgpu_mc_intr_nonstall_pause(g);
nvgpu_cic_intr_nonstall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause nonstall intr\n");
@@ -373,7 +374,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_mc_intr_stall_resume(g);
nvgpu_cic_intr_stall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != expected_stall_val) {
unit_return_fail(m, "failed to resume stall intr\n");
@@ -381,7 +382,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_mc_intr_nonstall_resume(g);
nvgpu_cic_intr_nonstall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != expected_nonstall_val) {
unit_return_fail(m, "failed to resume nonstall intr\n");
@@ -392,7 +393,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
/* mask all */
nvgpu_mc_intr_mask(g);
nvgpu_cic_intr_mask(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to mask stall intr\n");
@@ -405,7 +406,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* make this HAL NULL for branch coverage */
save_func = g->ops.mc.intr_mask;
g->ops.mc.intr_mask = NULL;
nvgpu_mc_intr_mask(g);
nvgpu_cic_intr_mask(g);
g->ops.mc.intr_mask = save_func;
return UNIT_SUCCESS;
@@ -448,7 +449,7 @@ int test_is_stall_and_eng_intr_pending(struct unit_module *m, struct gk20a *g,
/* test with everything pending */
for (i = 0U; i < NUM_MC_UNITS; i++) {
intrs_pending |= mc_units[i].bit;
if (mc_units[i].num == MC_INTR_UNIT_GR) {
if (mc_units[i].num == NVGPU_CIC_INTR_UNIT_GR) {
expected_eng_intr_pending = mc_units[i].bit;
}
}
@@ -663,18 +664,18 @@ int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
/* immediate completion */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* cause timeout */
nvgpu_posix_enable_fault_injection(cond_fi, true, 0);
/* wait on stall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* wait on nonstall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* disable the fault injection */
nvgpu_posix_enable_fault_injection(cond_fi, false, 0);