nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: PMU code cleanup

Browse Source 
-removed unsupported PMU f/w version defines &
corrected naming specific to chip
-removed unsupported PMU f/w version methods
which are not useful for existing ucode.
-removed unsupported PMU interface which are not
useful for existing ucode

Change-Id: I17933ff656f48a888e049d680f108b2ef7537439
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643399
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-01-22 13:06:41 +05:30
committed by mobile promotions
parent f3f14cdff5
commit 9f4cf27119
5 changed files with 15 additions and 845 deletions
Download Patch File Download Diff File Expand all files Collapse all files

733
drivers/gpu/nvgpu/common/pmu/pmu_fw.c
View File

@@ -36,31 +36,13 @@
#define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin" #define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin"
/* PMU F/W version */ /* PMU F/W version */
#define APP_VERSION_BIGGPU 22836594 #define APP_VERSION_GV11B 23355380
#define APP_VERSION_NC_3 23355380 #define APP_VERSION_GV10X 22836594
#define APP_VERSION_NC_2 20429989 #define APP_VERSION_GP10X 21308030
#define APP_VERSION_NC_1 20313802 #define APP_VERSION_GP10B 20429989
#define APP_VERSION_NC_0 20360931 #define APP_VERSION_GM20B 20490253
#define APP_VERSION_GM206 20652057
#define APP_VERSION_NV_GPU 21307569
#define APP_VERSION_NV_GPU_1 21308030
#define APP_VERSION_GM20B_5 20490253
#define APP_VERSION_GM20B_4 19008461
#define APP_VERSION_GM20B_3 18935575
#define APP_VERSION_GM20B_2 18694072
#define APP_VERSION_GM20B_1 18547257
#define APP_VERSION_GM20B 17615280
#define APP_VERSION_3 18357968
#define APP_VERSION_2 18542378
#define APP_VERSION_1 17997577 /*Obsolete this once 18357968 gets in*/
#define APP_VERSION_0 16856675
/* PMU version specific functions */ /* PMU version specific functions */
static u32 pmu_perfmon_cntr_sz_v0(struct nvgpu_pmu *pmu)
{
return sizeof(struct pmu_perfmon_counter_v0);
}
static u32 pmu_perfmon_cntr_sz_v2(struct nvgpu_pmu *pmu) static u32 pmu_perfmon_cntr_sz_v2(struct nvgpu_pmu *pmu)
{ {
return sizeof(struct pmu_perfmon_counter_v2); return sizeof(struct pmu_perfmon_counter_v2);
@@ -71,103 +53,31 @@ static void *get_perfmon_cntr_ptr_v2(struct nvgpu_pmu *pmu)
return (void *)(&pmu->perfmon_counter_v2); return (void *)(&pmu->perfmon_counter_v2);
} }
static void *get_perfmon_cntr_ptr_v0(struct nvgpu_pmu *pmu)
{
return (void *)(&pmu->perfmon_counter_v0);
}
static void set_perfmon_cntr_ut_v2(struct nvgpu_pmu *pmu, u16 ut) static void set_perfmon_cntr_ut_v2(struct nvgpu_pmu *pmu, u16 ut)
{ {
pmu->perfmon_counter_v2.upper_threshold = ut; pmu->perfmon_counter_v2.upper_threshold = ut;
} }
static void set_perfmon_cntr_ut_v0(struct nvgpu_pmu *pmu, u16 ut)
{
pmu->perfmon_counter_v0.upper_threshold = ut;
}
static void set_perfmon_cntr_lt_v2(struct nvgpu_pmu *pmu, u16 lt) static void set_perfmon_cntr_lt_v2(struct nvgpu_pmu *pmu, u16 lt)
{ {
pmu->perfmon_counter_v2.lower_threshold = lt; pmu->perfmon_counter_v2.lower_threshold = lt;
} }
static void set_perfmon_cntr_lt_v0(struct nvgpu_pmu *pmu, u16 lt)
{
pmu->perfmon_counter_v0.lower_threshold = lt;
}
static void set_perfmon_cntr_valid_v2(struct nvgpu_pmu *pmu, u8 valid) static void set_perfmon_cntr_valid_v2(struct nvgpu_pmu *pmu, u8 valid)
{ {
pmu->perfmon_counter_v2.valid = valid; pmu->perfmon_counter_v2.valid = valid;
} }
static void set_perfmon_cntr_valid_v0(struct nvgpu_pmu *pmu, u8 valid)
{
pmu->perfmon_counter_v0.valid = valid;
}
static void set_perfmon_cntr_index_v2(struct nvgpu_pmu *pmu, u8 index) static void set_perfmon_cntr_index_v2(struct nvgpu_pmu *pmu, u8 index)
{ {
pmu->perfmon_counter_v2.index = index; pmu->perfmon_counter_v2.index = index;
} }
static void set_perfmon_cntr_index_v0(struct nvgpu_pmu *pmu, u8 index)
{
pmu->perfmon_counter_v0.index = index;
}
static void set_perfmon_cntr_group_id_v2(struct nvgpu_pmu *pmu, u8 gid) static void set_perfmon_cntr_group_id_v2(struct nvgpu_pmu *pmu, u8 gid)
{ {
pmu->perfmon_counter_v2.group_id = gid; pmu->perfmon_counter_v2.group_id = gid;
} }
static void set_perfmon_cntr_group_id_v0(struct nvgpu_pmu *pmu, u8 gid)
{
pmu->perfmon_counter_v0.group_id = gid;
}
static u32 pmu_cmdline_size_v0(struct nvgpu_pmu *pmu)
{
return sizeof(struct pmu_cmdline_args_v0);
}
static u32 pmu_cmdline_size_v1(struct nvgpu_pmu *pmu)
{
return sizeof(struct pmu_cmdline_args_v1);
}
static u32 pmu_cmdline_size_v2(struct nvgpu_pmu *pmu)
{
return sizeof(struct pmu_cmdline_args_v2);
}
static void set_pmu_cmdline_args_cpufreq_v2(struct nvgpu_pmu *pmu, u32 freq)
{
pmu->args_v2.cpu_freq_hz = freq;
}
static void set_pmu_cmdline_args_secure_mode_v2(struct nvgpu_pmu *pmu, u32 val)
{
pmu->args_v2.secure_mode = val;
}
static void set_pmu_cmdline_args_falctracesize_v2(
struct nvgpu_pmu *pmu, u32 size)
{
pmu->args_v2.falc_trace_size = size;
}
static void set_pmu_cmdline_args_falctracedmabase_v2(struct nvgpu_pmu *pmu)
{
pmu->args_v2.falc_trace_dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
}
static void set_pmu_cmdline_args_falctracedmaidx_v2(
struct nvgpu_pmu *pmu, u32 idx)
{
pmu->args_v2.falc_trace_dma_idx = idx;
}
static void set_pmu_cmdline_args_falctracedmabase_v4(struct nvgpu_pmu *pmu) static void set_pmu_cmdline_args_falctracedmabase_v4(struct nvgpu_pmu *pmu)
{ {
pmu->args_v4.dma_addr.dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100; pmu->args_v4.dma_addr.dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
@@ -269,37 +179,6 @@ static void set_pmu_cmdline_args_falctracedmaidx_v3(
pmu->args_v3.falc_trace_dma_idx = idx; pmu->args_v3.falc_trace_dma_idx = idx;
} }
static void set_pmu_cmdline_args_cpufreq_v1(struct nvgpu_pmu *pmu, u32 freq)
{
pmu->args_v1.cpu_freq_hz = freq;
}
static void set_pmu_cmdline_args_secure_mode_v1(struct nvgpu_pmu *pmu, u32 val)
{
pmu->args_v1.secure_mode = val;
}
static void set_pmu_cmdline_args_falctracesize_v1(
struct nvgpu_pmu *pmu, u32 size)
{
pmu->args_v1.falc_trace_size = size;
}
static void set_pmu_cmdline_args_falctracedmabase_v1(struct nvgpu_pmu *pmu)
{
pmu->args_v1.falc_trace_dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
}
static void set_pmu_cmdline_args_falctracedmaidx_v1(
struct nvgpu_pmu *pmu, u32 idx)
{
pmu->args_v1.falc_trace_dma_idx = idx;
}
static void set_pmu_cmdline_args_cpufreq_v0(struct nvgpu_pmu *pmu, u32 freq)
{
pmu->args_v0.cpu_freq_hz = freq;
}
static void *get_pmu_cmdline_args_ptr_v4(struct nvgpu_pmu *pmu) static void *get_pmu_cmdline_args_ptr_v4(struct nvgpu_pmu *pmu)
{ {
return (void *)(&pmu->args_v4); return (void *)(&pmu->args_v4);
@@ -310,24 +189,10 @@ static void *get_pmu_cmdline_args_ptr_v3(struct nvgpu_pmu *pmu)
return (void *)(&pmu->args_v3); return (void *)(&pmu->args_v3);
} }
static void *get_pmu_cmdline_args_ptr_v2(struct nvgpu_pmu *pmu)
{
return (void *)(&pmu->args_v2);
}
static void *get_pmu_cmdline_args_ptr_v5(struct nvgpu_pmu *pmu) static void *get_pmu_cmdline_args_ptr_v5(struct nvgpu_pmu *pmu)
{ {
return (void *)(&pmu->args_v5); return (void *)(&pmu->args_v5);
} }
static void *get_pmu_cmdline_args_ptr_v1(struct nvgpu_pmu *pmu)
{
return (void *)(&pmu->args_v1);
}
static void *get_pmu_cmdline_args_ptr_v0(struct nvgpu_pmu *pmu)
{
return (void *)(&pmu->args_v0);
}
static u32 get_pmu_allocation_size_v3(struct nvgpu_pmu *pmu) static u32 get_pmu_allocation_size_v3(struct nvgpu_pmu *pmu)
{ {
@@ -344,11 +209,6 @@ static u32 get_pmu_allocation_size_v1(struct nvgpu_pmu *pmu)
return sizeof(struct pmu_allocation_v1); return sizeof(struct pmu_allocation_v1);
} }
static u32 get_pmu_allocation_size_v0(struct nvgpu_pmu *pmu)
{
return sizeof(struct pmu_allocation_v0);
}
static void set_pmu_allocation_ptr_v3(struct nvgpu_pmu *pmu, static void set_pmu_allocation_ptr_v3(struct nvgpu_pmu *pmu,
void **pmu_alloc_ptr, void *assign_ptr) void **pmu_alloc_ptr, void *assign_ptr)
{ {
@@ -376,15 +236,6 @@ static void set_pmu_allocation_ptr_v1(struct nvgpu_pmu *pmu,
*pmu_a_ptr = (struct pmu_allocation_v1 *)assign_ptr; *pmu_a_ptr = (struct pmu_allocation_v1 *)assign_ptr;
} }
static void set_pmu_allocation_ptr_v0(struct nvgpu_pmu *pmu,
void **pmu_alloc_ptr, void *assign_ptr)
{
struct pmu_allocation_v0 **pmu_a_ptr =
(struct pmu_allocation_v0 **)pmu_alloc_ptr;
*pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr;
}
static void pmu_allocation_set_dmem_size_v3(struct nvgpu_pmu *pmu, static void pmu_allocation_set_dmem_size_v3(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr, u16 size) void *pmu_alloc_ptr, u16 size)
{ {
@@ -412,15 +263,6 @@ static void pmu_allocation_set_dmem_size_v1(struct nvgpu_pmu *pmu,
pmu_a_ptr->alloc.dmem.size = size; pmu_a_ptr->alloc.dmem.size = size;
} }
static void pmu_allocation_set_dmem_size_v0(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr, u16 size)
{
struct pmu_allocation_v0 *pmu_a_ptr =
(struct pmu_allocation_v0 *)pmu_alloc_ptr;
pmu_a_ptr->alloc.dmem.size = size;
}
static u16 pmu_allocation_get_dmem_size_v3(struct nvgpu_pmu *pmu, static u16 pmu_allocation_get_dmem_size_v3(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr) void *pmu_alloc_ptr)
{ {
@@ -448,15 +290,6 @@ static u16 pmu_allocation_get_dmem_size_v1(struct nvgpu_pmu *pmu,
return pmu_a_ptr->alloc.dmem.size; return pmu_a_ptr->alloc.dmem.size;
} }
static u16 pmu_allocation_get_dmem_size_v0(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr)
{
struct pmu_allocation_v0 *pmu_a_ptr =
(struct pmu_allocation_v0 *)pmu_alloc_ptr;
return pmu_a_ptr->alloc.dmem.size;
}
static u32 pmu_allocation_get_dmem_offset_v3(struct nvgpu_pmu *pmu, static u32 pmu_allocation_get_dmem_offset_v3(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr) void *pmu_alloc_ptr)
{ {
@@ -484,15 +317,6 @@ static u32 pmu_allocation_get_dmem_offset_v1(struct nvgpu_pmu *pmu,
return pmu_a_ptr->alloc.dmem.offset; return pmu_a_ptr->alloc.dmem.offset;
} }
static u32 pmu_allocation_get_dmem_offset_v0(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr)
{
struct pmu_allocation_v0 *pmu_a_ptr =
(struct pmu_allocation_v0 *)pmu_alloc_ptr;
return pmu_a_ptr->alloc.dmem.offset;
}
static u32 *pmu_allocation_get_dmem_offset_addr_v3(struct nvgpu_pmu *pmu, static u32 *pmu_allocation_get_dmem_offset_addr_v3(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr) void *pmu_alloc_ptr)
{ {
@@ -538,15 +362,6 @@ static u32 *pmu_allocation_get_dmem_offset_addr_v1(struct nvgpu_pmu *pmu,
return &pmu_a_ptr->alloc.dmem.offset; return &pmu_a_ptr->alloc.dmem.offset;
} }
static u32 *pmu_allocation_get_dmem_offset_addr_v0(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr)
{
struct pmu_allocation_v0 *pmu_a_ptr =
(struct pmu_allocation_v0 *)pmu_alloc_ptr;
return &pmu_a_ptr->alloc.dmem.offset;
}
static void pmu_allocation_set_dmem_offset_v3(struct nvgpu_pmu *pmu, static void pmu_allocation_set_dmem_offset_v3(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr, u32 offset) void *pmu_alloc_ptr, u32 offset)
{ {
@@ -574,15 +389,6 @@ static void pmu_allocation_set_dmem_offset_v1(struct nvgpu_pmu *pmu,
pmu_a_ptr->alloc.dmem.offset = offset; pmu_a_ptr->alloc.dmem.offset = offset;
} }
static void pmu_allocation_set_dmem_offset_v0(struct nvgpu_pmu *pmu,
void *pmu_alloc_ptr, u32 offset)
{
struct pmu_allocation_v0 *pmu_a_ptr =
(struct pmu_allocation_v0 *)pmu_alloc_ptr;
pmu_a_ptr->alloc.dmem.offset = offset;
}
static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init) static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init)
{ {
return (void *)(&(init->pmu_init_v4)); return (void *)(&(init->pmu_init_v4));
@@ -625,27 +431,6 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v3(union pmu_init_msg_pmu *init_msg)
return init->sw_managed_area_size; return init->sw_managed_area_size;
} }
static void *get_pmu_msg_pmu_init_msg_ptr_v2(struct pmu_init_msg *init)
{
return (void *)(&(init->pmu_init_v2));
}
static u16 get_pmu_init_msg_pmu_sw_mg_off_v2(union pmu_init_msg_pmu *init_msg)
{
struct pmu_init_msg_pmu_v2 *init =
(struct pmu_init_msg_pmu_v2 *)(&init_msg->v1);
return init->sw_managed_area_offset;
}
static u16 get_pmu_init_msg_pmu_sw_mg_size_v2(union pmu_init_msg_pmu *init_msg)
{
struct pmu_init_msg_pmu_v2 *init =
(struct pmu_init_msg_pmu_v2 *)(&init_msg->v1);
return init->sw_managed_area_size;
}
static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init) static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init)
{ {
return (void *)(&(init->pmu_init_v1)); return (void *)(&(init->pmu_init_v1));
@@ -667,27 +452,6 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v1(union pmu_init_msg_pmu *init_msg)
return init->sw_managed_area_size; return init->sw_managed_area_size;
} }
static void *get_pmu_msg_pmu_init_msg_ptr_v0(struct pmu_init_msg *init)
{
return (void *)(&(init->pmu_init_v0));
}
static u16 get_pmu_init_msg_pmu_sw_mg_off_v0(union pmu_init_msg_pmu *init_msg)
{
struct pmu_init_msg_pmu_v0 *init =
(struct pmu_init_msg_pmu_v0 *)(&init_msg->v0);
return init->sw_managed_area_offset;
}
static u16 get_pmu_init_msg_pmu_sw_mg_size_v0(union pmu_init_msg_pmu *init_msg)
{
struct pmu_init_msg_pmu_v0 *init =
(struct pmu_init_msg_pmu_v0 *)(&init_msg->v0);
return init->sw_managed_area_size;
}
static u32 get_pmu_perfmon_cmd_start_size_v3(void) static u32 get_pmu_perfmon_cmd_start_size_v3(void)
{ {
return sizeof(struct pmu_perfmon_cmd_start_v3); return sizeof(struct pmu_perfmon_cmd_start_v3);
@@ -703,11 +467,6 @@ static u32 get_pmu_perfmon_cmd_start_size_v1(void)
return sizeof(struct pmu_perfmon_cmd_start_v1); return sizeof(struct pmu_perfmon_cmd_start_v1);
} }
static u32 get_pmu_perfmon_cmd_start_size_v0(void)
{
return sizeof(struct pmu_perfmon_cmd_start_v0);
}
static int get_perfmon_cmd_start_offsetofvar_v3( static int get_perfmon_cmd_start_offsetofvar_v3(
enum pmu_perfmon_cmd_start_fields field) enum pmu_perfmon_cmd_start_fields field)
{ {
@@ -750,20 +509,6 @@ static int get_perfmon_cmd_start_offsetofvar_v1(
return 0; return 0;
} }
static int get_perfmon_cmd_start_offsetofvar_v0(
enum pmu_perfmon_cmd_start_fields field)
{
switch (field) {
case COUNTER_ALLOC:
return offsetof(struct pmu_perfmon_cmd_start_v0,
counter_alloc);
default:
return -EINVAL;
}
return 0;
}
static u32 get_pmu_perfmon_cmd_init_size_v3(void) static u32 get_pmu_perfmon_cmd_init_size_v3(void)
{ {
return sizeof(struct pmu_perfmon_cmd_init_v3); return sizeof(struct pmu_perfmon_cmd_init_v3);
@@ -779,11 +524,6 @@ static u32 get_pmu_perfmon_cmd_init_size_v1(void)
return sizeof(struct pmu_perfmon_cmd_init_v1); return sizeof(struct pmu_perfmon_cmd_init_v1);
} }
static u32 get_pmu_perfmon_cmd_init_size_v0(void)
{
return sizeof(struct pmu_perfmon_cmd_init_v0);
}
static int get_perfmon_cmd_init_offsetofvar_v3( static int get_perfmon_cmd_init_offsetofvar_v3(
enum pmu_perfmon_cmd_start_fields field) enum pmu_perfmon_cmd_start_fields field)
{ {
@@ -826,20 +566,6 @@ static int get_perfmon_cmd_init_offsetofvar_v1(
return 0; return 0;
} }
static int get_perfmon_cmd_init_offsetofvar_v0(
enum pmu_perfmon_cmd_start_fields field)
{
switch (field) {
case COUNTER_ALLOC:
return offsetof(struct pmu_perfmon_cmd_init_v0,
counter_alloc);
default:
return -EINVAL;
}
return 0;
}
static void perfmon_start_set_cmd_type_v3(struct pmu_perfmon_cmd *pc, u8 value) static void perfmon_start_set_cmd_type_v3(struct pmu_perfmon_cmd *pc, u8 value)
{ {
struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -861,13 +587,6 @@ static void perfmon_start_set_cmd_type_v1(struct pmu_perfmon_cmd *pc, u8 value)
start->cmd_type = value; start->cmd_type = value;
} }
static void perfmon_start_set_cmd_type_v0(struct pmu_perfmon_cmd *pc, u8 value)
{
struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
start->cmd_type = value;
}
static void perfmon_start_set_group_id_v3(struct pmu_perfmon_cmd *pc, u8 value) static void perfmon_start_set_group_id_v3(struct pmu_perfmon_cmd *pc, u8 value)
{ {
struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -889,13 +608,6 @@ static void perfmon_start_set_group_id_v1(struct pmu_perfmon_cmd *pc, u8 value)
start->group_id = value; start->group_id = value;
} }
static void perfmon_start_set_group_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
{
struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
start->group_id = value;
}
static void perfmon_start_set_state_id_v3(struct pmu_perfmon_cmd *pc, u8 value) static void perfmon_start_set_state_id_v3(struct pmu_perfmon_cmd *pc, u8 value)
{ {
struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -917,13 +629,6 @@ static void perfmon_start_set_state_id_v1(struct pmu_perfmon_cmd *pc, u8 value)
start->state_id = value; start->state_id = value;
} }
static void perfmon_start_set_state_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
{
struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
start->state_id = value;
}
static void perfmon_start_set_flags_v3(struct pmu_perfmon_cmd *pc, u8 value) static void perfmon_start_set_flags_v3(struct pmu_perfmon_cmd *pc, u8 value)
{ {
struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -945,13 +650,6 @@ static void perfmon_start_set_flags_v1(struct pmu_perfmon_cmd *pc, u8 value)
start->flags = value; start->flags = value;
} }
static void perfmon_start_set_flags_v0(struct pmu_perfmon_cmd *pc, u8 value)
{
struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
start->flags = value;
}
static u8 perfmon_start_get_flags_v3(struct pmu_perfmon_cmd *pc) static u8 perfmon_start_get_flags_v3(struct pmu_perfmon_cmd *pc)
{ {
struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
@@ -973,13 +671,6 @@ static u8 perfmon_start_get_flags_v1(struct pmu_perfmon_cmd *pc)
return start->flags; return start->flags;
} }
static u8 perfmon_start_get_flags_v0(struct pmu_perfmon_cmd *pc)
{
struct pmu_perfmon_cmd_start_v0 *start = &pc->start_v0;
return start->flags;
}
static void perfmon_cmd_init_set_sample_buffer_v3(struct pmu_perfmon_cmd *pc, static void perfmon_cmd_init_set_sample_buffer_v3(struct pmu_perfmon_cmd *pc,
u16 value) u16 value)
{ {
@@ -1005,14 +696,6 @@ static void perfmon_cmd_init_set_sample_buffer_v1(struct pmu_perfmon_cmd *pc,
init->sample_buffer = value; init->sample_buffer = value;
} }
static void perfmon_cmd_init_set_sample_buffer_v0(struct pmu_perfmon_cmd *pc,
u16 value)
{
struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
init->sample_buffer = value;
}
static void perfmon_cmd_init_set_dec_cnt_v3(struct pmu_perfmon_cmd *pc, static void perfmon_cmd_init_set_dec_cnt_v3(struct pmu_perfmon_cmd *pc,
u8 value) u8 value)
{ {
@@ -1037,14 +720,6 @@ static void perfmon_cmd_init_set_dec_cnt_v1(struct pmu_perfmon_cmd *pc,
init->to_decrease_count = value; init->to_decrease_count = value;
} }
static void perfmon_cmd_init_set_dec_cnt_v0(struct pmu_perfmon_cmd *pc,
u8 value)
{
struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
init->to_decrease_count = value;
}
static void perfmon_cmd_init_set_base_cnt_id_v3(struct pmu_perfmon_cmd *pc, static void perfmon_cmd_init_set_base_cnt_id_v3(struct pmu_perfmon_cmd *pc,
u8 value) u8 value)
{ {
@@ -1069,14 +744,6 @@ static void perfmon_cmd_init_set_base_cnt_id_v1(struct pmu_perfmon_cmd *pc,
init->base_counter_id = value; init->base_counter_id = value;
} }
static void perfmon_cmd_init_set_base_cnt_id_v0(struct pmu_perfmon_cmd *pc,
u8 value)
{
struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
init->base_counter_id = value;
}
static void perfmon_cmd_init_set_samp_period_us_v3(struct pmu_perfmon_cmd *pc, static void perfmon_cmd_init_set_samp_period_us_v3(struct pmu_perfmon_cmd *pc,
u32 value) u32 value)
{ {
@@ -1101,14 +768,6 @@ static void perfmon_cmd_init_set_samp_period_us_v1(struct pmu_perfmon_cmd *pc,
init->sample_period_us = value; init->sample_period_us = value;
} }
static void perfmon_cmd_init_set_samp_period_us_v0(struct pmu_perfmon_cmd *pc,
u32 value)
{
struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
init->sample_period_us = value;
}
static void perfmon_cmd_init_set_num_cnt_v3(struct pmu_perfmon_cmd *pc, static void perfmon_cmd_init_set_num_cnt_v3(struct pmu_perfmon_cmd *pc,
u8 value) u8 value)
{ {
@@ -1133,14 +792,6 @@ static void perfmon_cmd_init_set_num_cnt_v1(struct pmu_perfmon_cmd *pc,
init->num_counters = value; init->num_counters = value;
} }
static void perfmon_cmd_init_set_num_cnt_v0(struct pmu_perfmon_cmd *pc,
u8 value)
{
struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
init->num_counters = value;
}
static void perfmon_cmd_init_set_mov_avg_v3(struct pmu_perfmon_cmd *pc, static void perfmon_cmd_init_set_mov_avg_v3(struct pmu_perfmon_cmd *pc,
u8 value) u8 value)
{ {
@@ -1165,25 +816,6 @@ static void perfmon_cmd_init_set_mov_avg_v1(struct pmu_perfmon_cmd *pc,
init->samples_in_moving_avg = value; init->samples_in_moving_avg = value;
} }
static void perfmon_cmd_init_set_mov_avg_v0(struct pmu_perfmon_cmd *pc,
u8 value)
{
struct pmu_perfmon_cmd_init_v0 *init = &pc->init_v0;
init->samples_in_moving_avg = value;
}
static void get_pmu_init_msg_pmu_queue_params_v0(struct pmu_queue *queue,
u32 id, void *pmu_init_msg)
{
struct pmu_init_msg_pmu_v0 *init =
(struct pmu_init_msg_pmu_v0 *)pmu_init_msg;
queue->index = init->queue_info[id].index;
queue->offset = init->queue_info[id].offset;
queue->size = init->queue_info[id].size;
}
static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue, static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue,
u32 id, void *pmu_init_msg) u32 id, void *pmu_init_msg)
{ {
@@ -1195,17 +827,6 @@ static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue,
queue->size = init->queue_info[id].size; queue->size = init->queue_info[id].size;
} }
static void get_pmu_init_msg_pmu_queue_params_v2(struct pmu_queue *queue,
u32 id, void *pmu_init_msg)
{
struct pmu_init_msg_pmu_v2 *init =
(struct pmu_init_msg_pmu_v2 *)pmu_init_msg;
queue->index = init->queue_info[id].index;
queue->offset = init->queue_info[id].offset;
queue->size = init->queue_info[id].size;
}
static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue, static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue,
u32 id, void *pmu_init_msg) u32 id, void *pmu_init_msg)
{ {
@@ -1294,11 +915,6 @@ static void *get_pmu_sequence_in_alloc_ptr_v1(struct pmu_sequence *seq)
return (void *)(&seq->in_v1); return (void *)(&seq->in_v1);
} }
static void *get_pmu_sequence_in_alloc_ptr_v0(struct pmu_sequence *seq)
{
return (void *)(&seq->in_v0);
}
static void *get_pmu_sequence_out_alloc_ptr_v3(struct pmu_sequence *seq) static void *get_pmu_sequence_out_alloc_ptr_v3(struct pmu_sequence *seq)
{ {
return (void *)(&seq->out_v3); return (void *)(&seq->out_v3);
@@ -1309,11 +925,6 @@ static void *get_pmu_sequence_out_alloc_ptr_v1(struct pmu_sequence *seq)
return (void *)(&seq->out_v1); return (void *)(&seq->out_v1);
} }
static void *get_pmu_sequence_out_alloc_ptr_v0(struct pmu_sequence *seq)
{
return (void *)(&seq->out_v0);
}
static u8 pg_cmd_eng_buf_load_size_v0(struct pmu_pg_cmd *pg) static u8 pg_cmd_eng_buf_load_size_v0(struct pmu_pg_cmd *pg)
{ {
return sizeof(pg->eng_buf_load_v0); return sizeof(pg->eng_buf_load_v0);
@@ -1472,9 +1083,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
switch (pmu->desc->app_version) { switch (pmu->desc->app_version) {
case APP_VERSION_NC_2: case APP_VERSION_GP10B:
case APP_VERSION_NC_1:
case APP_VERSION_NC_0:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size = g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v1; pg_cmd_eng_buf_load_size_v1;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1576,8 +1185,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
g->ops.pmu_ver.get_pmu_seq_out_a_ptr = g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v1; get_pmu_sequence_out_alloc_ptr_v1;
break; break;
case APP_VERSION_NC_3: case APP_VERSION_GV11B:
case APP_VERSION_BIGGPU: case APP_VERSION_GV10X:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size = g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v2; pg_cmd_eng_buf_load_size_v2;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1640,7 +1249,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
pmu_allocation_get_fb_addr_v3; pmu_allocation_get_fb_addr_v3;
g->ops.pmu_ver.pmu_allocation_get_fb_size = g->ops.pmu_ver.pmu_allocation_get_fb_size =
pmu_allocation_get_fb_size_v3; pmu_allocation_get_fb_size_v3;
if (pmu->desc->app_version == APP_VERSION_BIGGPU) if (pmu->desc->app_version == APP_VERSION_GV10X)
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v5; get_pmu_init_msg_pmu_queue_params_v5;
else else
@@ -1687,9 +1296,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
g->ops.pmu_ver.get_pmu_seq_out_a_ptr = g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v3; get_pmu_sequence_out_alloc_ptr_v3;
break; break;
case APP_VERSION_GM206: case APP_VERSION_GP10X:
case APP_VERSION_NV_GPU:
case APP_VERSION_NV_GPU_1:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size = g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v2; pg_cmd_eng_buf_load_size_v2;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1752,17 +1359,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
pmu_allocation_get_fb_addr_v3; pmu_allocation_get_fb_addr_v3;
g->ops.pmu_ver.pmu_allocation_get_fb_size = g->ops.pmu_ver.pmu_allocation_get_fb_size =
pmu_allocation_get_fb_size_v3; pmu_allocation_get_fb_size_v3;
if (pmu->desc->app_version != APP_VERSION_NV_GPU &&
pmu->desc->app_version != APP_VERSION_NV_GPU_1) {
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v2;
g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
get_pmu_msg_pmu_init_msg_ptr_v2;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
get_pmu_init_msg_pmu_sw_mg_off_v2;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
get_pmu_init_msg_pmu_sw_mg_size_v2;
} else {
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v3; get_pmu_init_msg_pmu_queue_params_v3;
g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
@@ -1771,7 +1367,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
get_pmu_init_msg_pmu_sw_mg_off_v3; get_pmu_init_msg_pmu_sw_mg_off_v3;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
get_pmu_init_msg_pmu_sw_mg_size_v3; get_pmu_init_msg_pmu_sw_mg_size_v3;
}
g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
get_pmu_perfmon_cmd_start_size_v3; get_pmu_perfmon_cmd_start_size_v3;
g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
@@ -1807,8 +1402,7 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
g->ops.pmu_ver.get_pmu_seq_out_a_ptr = g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v3; get_pmu_sequence_out_alloc_ptr_v3;
break; break;
case APP_VERSION_GM20B_5: case APP_VERSION_GM20B:
case APP_VERSION_GM20B_4:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size = g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v0; pg_cmd_eng_buf_load_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
@@ -1910,311 +1504,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu)
g->ops.pmu_ver.get_pmu_seq_out_a_ptr = g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v1; get_pmu_sequence_out_alloc_ptr_v1;
break; break;
case APP_VERSION_GM20B_3:
case APP_VERSION_GM20B_2:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
pg_cmd_eng_buf_load_set_cmd_type_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
pg_cmd_eng_buf_load_set_engine_id_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
pg_cmd_eng_buf_load_set_buf_idx_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
pg_cmd_eng_buf_load_set_pad_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
pg_cmd_eng_buf_load_set_buf_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
pg_cmd_eng_buf_load_set_dma_base_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
pg_cmd_eng_buf_load_set_dma_offset_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
pg_cmd_eng_buf_load_set_dma_idx_v0;
g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
g->ops.pmu_ver.set_perfmon_cntr_valid =
set_perfmon_cntr_valid_v2;
g->ops.pmu_ver.set_perfmon_cntr_index =
set_perfmon_cntr_index_v2;
g->ops.pmu_ver.set_perfmon_cntr_group_id =
set_perfmon_cntr_group_id_v2;
g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
g->pmu_ver_cmd_id_zbc_table_update = 16;
__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
g->ops.pmu_ver.get_pmu_cmdline_args_size =
pmu_cmdline_size_v2;
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
set_pmu_cmdline_args_cpufreq_v2;
g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
set_pmu_cmdline_args_secure_mode_v2;
g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
set_pmu_cmdline_args_falctracesize_v2;
g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
set_pmu_cmdline_args_falctracedmabase_v2;
g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
set_pmu_cmdline_args_falctracedmaidx_v2;
g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
get_pmu_cmdline_args_ptr_v2;
g->ops.pmu_ver.get_pmu_allocation_struct_size =
get_pmu_allocation_size_v1;
g->ops.pmu_ver.set_pmu_allocation_ptr =
set_pmu_allocation_ptr_v1;
g->ops.pmu_ver.pmu_allocation_set_dmem_size =
pmu_allocation_set_dmem_size_v1;
g->ops.pmu_ver.pmu_allocation_get_dmem_size =
pmu_allocation_get_dmem_size_v1;
g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
pmu_allocation_get_dmem_offset_v1;
g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
pmu_allocation_get_dmem_offset_addr_v1;
g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
pmu_allocation_set_dmem_offset_v1;
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v1;
g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
get_pmu_msg_pmu_init_msg_ptr_v1;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
get_pmu_init_msg_pmu_sw_mg_off_v1;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
get_pmu_init_msg_pmu_sw_mg_size_v1;
g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
get_pmu_perfmon_cmd_start_size_v1;
g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
get_perfmon_cmd_start_offsetofvar_v1;
g->ops.pmu_ver.perfmon_start_set_cmd_type =
perfmon_start_set_cmd_type_v1;
g->ops.pmu_ver.perfmon_start_set_group_id =
perfmon_start_set_group_id_v1;
g->ops.pmu_ver.perfmon_start_set_state_id =
perfmon_start_set_state_id_v1;
g->ops.pmu_ver.perfmon_start_set_flags =
perfmon_start_set_flags_v1;
g->ops.pmu_ver.perfmon_start_get_flags =
perfmon_start_get_flags_v1;
g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
get_pmu_perfmon_cmd_init_size_v1;
g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
get_perfmon_cmd_init_offsetofvar_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
perfmon_cmd_init_set_sample_buffer_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
perfmon_cmd_init_set_dec_cnt_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
perfmon_cmd_init_set_base_cnt_id_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
perfmon_cmd_init_set_samp_period_us_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
perfmon_cmd_init_set_num_cnt_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
perfmon_cmd_init_set_mov_avg_v1;
g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
get_pmu_sequence_in_alloc_ptr_v1;
g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v1;
break;
case APP_VERSION_GM20B_1:
case APP_VERSION_GM20B:
case APP_VERSION_1:
case APP_VERSION_2:
case APP_VERSION_3:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
pg_cmd_eng_buf_load_set_cmd_type_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
pg_cmd_eng_buf_load_set_engine_id_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
pg_cmd_eng_buf_load_set_buf_idx_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
pg_cmd_eng_buf_load_set_pad_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
pg_cmd_eng_buf_load_set_buf_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
pg_cmd_eng_buf_load_set_dma_base_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
pg_cmd_eng_buf_load_set_dma_offset_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
pg_cmd_eng_buf_load_set_dma_idx_v0;
g->pmu_ver_cmd_id_zbc_table_update = 16;
__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
g->ops.pmu_ver.set_perfmon_cntr_valid =
set_perfmon_cntr_valid_v0;
g->ops.pmu_ver.set_perfmon_cntr_index =
set_perfmon_cntr_index_v0;
g->ops.pmu_ver.set_perfmon_cntr_group_id =
set_perfmon_cntr_group_id_v0;
g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v0;
g->ops.pmu_ver.get_pmu_cmdline_args_size =
pmu_cmdline_size_v1;
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
set_pmu_cmdline_args_cpufreq_v1;
g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
set_pmu_cmdline_args_secure_mode_v1;
g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
set_pmu_cmdline_args_falctracesize_v1;
g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
set_pmu_cmdline_args_falctracedmabase_v1;
g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
set_pmu_cmdline_args_falctracedmaidx_v1;
g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
get_pmu_cmdline_args_ptr_v1;
g->ops.pmu_ver.get_pmu_allocation_struct_size =
get_pmu_allocation_size_v1;
g->ops.pmu_ver.set_pmu_allocation_ptr =
set_pmu_allocation_ptr_v1;
g->ops.pmu_ver.pmu_allocation_set_dmem_size =
pmu_allocation_set_dmem_size_v1;
g->ops.pmu_ver.pmu_allocation_get_dmem_size =
pmu_allocation_get_dmem_size_v1;
g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
pmu_allocation_get_dmem_offset_v1;
g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
pmu_allocation_get_dmem_offset_addr_v1;
g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
pmu_allocation_set_dmem_offset_v1;
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v1;
g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
get_pmu_msg_pmu_init_msg_ptr_v1;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
get_pmu_init_msg_pmu_sw_mg_off_v1;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
get_pmu_init_msg_pmu_sw_mg_size_v1;
g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
get_pmu_perfmon_cmd_start_size_v1;
g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
get_perfmon_cmd_start_offsetofvar_v1;
g->ops.pmu_ver.perfmon_start_set_cmd_type =
perfmon_start_set_cmd_type_v1;
g->ops.pmu_ver.perfmon_start_set_group_id =
perfmon_start_set_group_id_v1;
g->ops.pmu_ver.perfmon_start_set_state_id =
perfmon_start_set_state_id_v1;
g->ops.pmu_ver.perfmon_start_set_flags =
perfmon_start_set_flags_v1;
g->ops.pmu_ver.perfmon_start_get_flags =
perfmon_start_get_flags_v1;
g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
get_pmu_perfmon_cmd_init_size_v1;
g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
get_perfmon_cmd_init_offsetofvar_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
perfmon_cmd_init_set_sample_buffer_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
perfmon_cmd_init_set_dec_cnt_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
perfmon_cmd_init_set_base_cnt_id_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
perfmon_cmd_init_set_samp_period_us_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
perfmon_cmd_init_set_num_cnt_v1;
g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
perfmon_cmd_init_set_mov_avg_v1;
g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
get_pmu_sequence_in_alloc_ptr_v1;
g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v1;
break;
case APP_VERSION_0:
g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
pg_cmd_eng_buf_load_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
pg_cmd_eng_buf_load_set_cmd_type_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
pg_cmd_eng_buf_load_set_engine_id_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
pg_cmd_eng_buf_load_set_buf_idx_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
pg_cmd_eng_buf_load_set_pad_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
pg_cmd_eng_buf_load_set_buf_size_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
pg_cmd_eng_buf_load_set_dma_base_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
pg_cmd_eng_buf_load_set_dma_offset_v0;
g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
pg_cmd_eng_buf_load_set_dma_idx_v0;
g->pmu_ver_cmd_id_zbc_table_update = 14;
__nvgpu_set_enabled(g, NVGPU_PMU_ZBC_SAVE, true);
g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
g->ops.pmu_ver.set_perfmon_cntr_valid =
set_perfmon_cntr_valid_v0;
g->ops.pmu_ver.set_perfmon_cntr_index =
set_perfmon_cntr_index_v0;
g->ops.pmu_ver.set_perfmon_cntr_group_id =
set_perfmon_cntr_group_id_v0;
g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v0;
g->ops.pmu_ver.get_pmu_cmdline_args_size =
pmu_cmdline_size_v0;
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
set_pmu_cmdline_args_cpufreq_v0;
g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
NULL;
g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
get_pmu_cmdline_args_ptr_v0;
g->ops.pmu_ver.get_pmu_allocation_struct_size =
get_pmu_allocation_size_v0;
g->ops.pmu_ver.set_pmu_allocation_ptr =
set_pmu_allocation_ptr_v0;
g->ops.pmu_ver.pmu_allocation_set_dmem_size =
pmu_allocation_set_dmem_size_v0;
g->ops.pmu_ver.pmu_allocation_get_dmem_size =
pmu_allocation_get_dmem_size_v0;
g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
pmu_allocation_get_dmem_offset_v0;
g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
pmu_allocation_get_dmem_offset_addr_v0;
g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
pmu_allocation_set_dmem_offset_v0;
g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
get_pmu_init_msg_pmu_queue_params_v0;
g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
get_pmu_msg_pmu_init_msg_ptr_v0;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
get_pmu_init_msg_pmu_sw_mg_off_v0;
g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
get_pmu_init_msg_pmu_sw_mg_size_v0;
g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
get_pmu_perfmon_cmd_start_size_v0;
g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
get_perfmon_cmd_start_offsetofvar_v0;
g->ops.pmu_ver.perfmon_start_set_cmd_type =
perfmon_start_set_cmd_type_v0;
g->ops.pmu_ver.perfmon_start_set_group_id =
perfmon_start_set_group_id_v0;
g->ops.pmu_ver.perfmon_start_set_state_id =
perfmon_start_set_state_id_v0;
g->ops.pmu_ver.perfmon_start_set_flags =
perfmon_start_set_flags_v0;
g->ops.pmu_ver.perfmon_start_get_flags =
perfmon_start_get_flags_v0;
g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
get_pmu_perfmon_cmd_init_size_v0;
g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
get_perfmon_cmd_init_offsetofvar_v0;
g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
perfmon_cmd_init_set_sample_buffer_v0;
g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
perfmon_cmd_init_set_dec_cnt_v0;
g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
perfmon_cmd_init_set_base_cnt_id_v0;
g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
perfmon_cmd_init_set_samp_period_us_v0;
g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
perfmon_cmd_init_set_num_cnt_v0;
g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
perfmon_cmd_init_set_mov_avg_v0;
g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
get_pmu_sequence_in_alloc_ptr_v0;
g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
get_pmu_sequence_out_alloc_ptr_v0;
break;
default: default:
nvgpu_err(g, "PMU code version not supported version: %d\n", nvgpu_err(g, "PMU code version not supported version: %d\n",
pmu->desc->app_version); pmu->desc->app_version);

21
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
View File

@@ -41,12 +41,6 @@ struct falc_dma_addr {
u8 dma_offset; u8 dma_offset;
}; };
struct pmu_mem_v0 {
u32 dma_base;
u8 dma_offset;
u8 dma_idx;
};
struct pmu_mem_v1 { struct pmu_mem_v1 {
u32 dma_base; u32 dma_base;
u8 dma_offset; u8 dma_offset;
@@ -54,12 +48,6 @@ struct pmu_mem_v1 {
u16 fb_size; u16 fb_size;
}; };
struct pmu_mem_v2 {
struct falc_dma_addr dma_addr;
u8 dma_idx;
u16 fb_size;
};
struct pmu_mem_desc_v0 { struct pmu_mem_desc_v0 {
struct falc_u64 dma_addr; struct falc_u64 dma_addr;
u16 dma_sizemax; u16 dma_sizemax;
@@ -78,15 +66,6 @@ struct flcn_mem_desc_v0 {
#define nv_flcn_mem_desc flcn_mem_desc_v0 #define nv_flcn_mem_desc flcn_mem_desc_v0
struct pmu_allocation_v0 {
u8 pad[3];
u8 fb_mem_use;
struct {
struct pmu_dmem dmem;
struct pmu_mem_v0 fb;
} alloc;
};
struct pmu_allocation_v1 { struct pmu_allocation_v1 {
struct { struct {
struct pmu_dmem dmem; struct pmu_dmem dmem;

6
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -269,14 +269,12 @@ struct pmu_sequence {
u32 desc; u32 desc;
struct pmu_msg *msg; struct pmu_msg *msg;
union { union {
struct pmu_allocation_v0 in_v0;
struct pmu_allocation_v1 in_v1; struct pmu_allocation_v1 in_v1;
struct pmu_allocation_v2 in_v2; struct pmu_allocation_v2 in_v2;
struct pmu_allocation_v3 in_v3; struct pmu_allocation_v3 in_v3;
}; };
struct nvgpu_mem *in_mem; struct nvgpu_mem *in_mem;
union { union {
struct pmu_allocation_v0 out_v0;
struct pmu_allocation_v1 out_v1; struct pmu_allocation_v1 out_v1;
struct pmu_allocation_v2 out_v2; struct pmu_allocation_v2 out_v2;
struct pmu_allocation_v3 out_v3; struct pmu_allocation_v3 out_v3;
@@ -351,7 +349,6 @@ struct nvgpu_pmu {
union { union {
struct pmu_perfmon_counter_v2 perfmon_counter_v2; struct pmu_perfmon_counter_v2 perfmon_counter_v2;
struct pmu_perfmon_counter_v0 perfmon_counter_v0;
}; };
u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM]; u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
@@ -371,9 +368,6 @@ struct nvgpu_pmu {
bool zbc_ready; bool zbc_ready;
union { union {
struct pmu_cmdline_args_v0 args_v0;
struct pmu_cmdline_args_v1 args_v1;
struct pmu_cmdline_args_v2 args_v2;
struct pmu_cmdline_args_v3 args_v3; struct pmu_cmdline_args_v3 args_v3;
struct pmu_cmdline_args_v4 args_v4; struct pmu_cmdline_args_v4 args_v4;
struct pmu_cmdline_args_v5 args_v5; struct pmu_cmdline_args_v5 args_v5;

30
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
View File

@@ -44,15 +44,6 @@ enum {
PMU_PERFMON_CMD_ID_INIT = 2 PMU_PERFMON_CMD_ID_INIT = 2
}; };
struct pmu_perfmon_counter_v0 {
u8 index;
u8 flags;
u8 group_id;
u8 valid;
u16 upper_threshold; /* units of 0.01% */
u16 lower_threshold; /* units of 0.01% */
};
struct pmu_perfmon_counter_v2 { struct pmu_perfmon_counter_v2 {
u8 index; u8 index;
u8 flags; u8 flags;
@@ -96,14 +87,6 @@ struct pmu_perfmon_cmd_start_v1 {
struct pmu_allocation_v1 counter_alloc; struct pmu_allocation_v1 counter_alloc;
}; };
struct pmu_perfmon_cmd_start_v0 {
u8 cmd_type;
u8 group_id;
u8 state_id;
u8 flags;
struct pmu_allocation_v0 counter_alloc;
};
struct pmu_perfmon_cmd_stop { struct pmu_perfmon_cmd_stop {
u8 cmd_type; u8 cmd_type;
}; };
@@ -141,26 +124,13 @@ struct pmu_perfmon_cmd_init_v1 {
u16 sample_buffer; u16 sample_buffer;
}; };
struct pmu_perfmon_cmd_init_v0 {
u8 cmd_type;
u8 to_decrease_count;
u8 base_counter_id;
u32 sample_period_us;
struct pmu_allocation_v0 counter_alloc;
u8 num_counters;
u8 samples_in_moving_avg;
u16 sample_buffer;
};
struct pmu_perfmon_cmd { struct pmu_perfmon_cmd {
union { union {
u8 cmd_type; u8 cmd_type;
struct pmu_perfmon_cmd_start_v0 start_v0;
struct pmu_perfmon_cmd_start_v1 start_v1; struct pmu_perfmon_cmd_start_v1 start_v1;
struct pmu_perfmon_cmd_start_v2 start_v2; struct pmu_perfmon_cmd_start_v2 start_v2;
struct pmu_perfmon_cmd_start_v3 start_v3; struct pmu_perfmon_cmd_start_v3 start_v3;
struct pmu_perfmon_cmd_stop stop; struct pmu_perfmon_cmd_stop stop;
struct pmu_perfmon_cmd_init_v0 init_v0;
struct pmu_perfmon_cmd_init_v1 init_v1; struct pmu_perfmon_cmd_init_v1 init_v1;
struct pmu_perfmon_cmd_init_v2 init_v2; struct pmu_perfmon_cmd_init_v2 init_v2;
struct pmu_perfmon_cmd_init_v3 init_v3; struct pmu_perfmon_cmd_init_v3 init_v3;

62
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
View File

@@ -26,33 +26,6 @@
#include "gpmuif_cmn.h" #include "gpmuif_cmn.h"
/* Make sure size of this structure is a multiple of 4 bytes */ /* Make sure size of this structure is a multiple of 4 bytes */
struct pmu_cmdline_args_v0 {
u32 cpu_freq_hz;
u32 falc_trace_size;
u32 falc_trace_dma_base;
u32 falc_trace_dma_idx;
struct pmu_mem_v0 gc6_ctx;
};
struct pmu_cmdline_args_v1 {
u32 cpu_freq_hz;
u32 falc_trace_size;
u32 falc_trace_dma_base;
u32 falc_trace_dma_idx;
u8 secure_mode;
struct pmu_mem_v1 gc6_ctx;
};
struct pmu_cmdline_args_v2 {
u32 cpu_freq_hz;
u32 falc_trace_size;
u32 falc_trace_dma_base;
u32 falc_trace_dma_idx;
u8 secure_mode;
u8 raise_priv_sec;
struct pmu_mem_v1 gc6_ctx;
};
struct pmu_cmdline_args_v3 { struct pmu_cmdline_args_v3 {
u32 reserved; u32 reserved;
u32 cpu_freq_hz; u32 cpu_freq_hz;
@@ -118,21 +91,6 @@ enum {
PMU_INIT_MSG_TYPE_PMU_INIT = 0, PMU_INIT_MSG_TYPE_PMU_INIT = 0,
}; };
struct pmu_init_msg_pmu_v0 {
u8 msg_type;
u8 pad;
struct {
u16 size;
u16 offset;
u8 index;
u8 pad;
} queue_info[PMU_QUEUE_COUNT];
u16 sw_managed_area_offset;
u16 sw_managed_area_size;
};
struct pmu_init_msg_pmu_v1 { struct pmu_init_msg_pmu_v1 {
u8 msg_type; u8 msg_type;
u8 pad; u8 pad;
@@ -148,22 +106,6 @@ struct pmu_init_msg_pmu_v1 {
u16 sw_managed_area_offset; u16 sw_managed_area_offset;
u16 sw_managed_area_size; u16 sw_managed_area_size;
}; };
struct pmu_init_msg_pmu_v2 {
u8 msg_type;
u8 pad;
u16 os_debug_entry_point;
struct {
u16 size;
u16 offset;
u8 index;
u8 pad;
} queue_info[PMU_QUEUE_COUNT];
u16 sw_managed_area_offset;
u16 sw_managed_area_size;
u8 dummy[18];
};
#define PMU_QUEUE_COUNT_FOR_V4 5 #define PMU_QUEUE_COUNT_FOR_V4 5
#define PMU_QUEUE_COUNT_FOR_V3 3 #define PMU_QUEUE_COUNT_FOR_V3 3
@@ -200,9 +142,7 @@ struct pmu_init_msg_pmu_v4 {
}; };
union pmu_init_msg_pmu { union pmu_init_msg_pmu {
struct pmu_init_msg_pmu_v0 v0;
struct pmu_init_msg_pmu_v1 v1; struct pmu_init_msg_pmu_v1 v1;
struct pmu_init_msg_pmu_v2 v2;
struct pmu_init_msg_pmu_v3 v3; struct pmu_init_msg_pmu_v3 v3;
struct pmu_init_msg_pmu_v4 v4; struct pmu_init_msg_pmu_v4 v4;
}; };
@@ -211,8 +151,6 @@ struct pmu_init_msg {
union { union {
u8 msg_type; u8 msg_type;
struct pmu_init_msg_pmu_v1 pmu_init_v1; struct pmu_init_msg_pmu_v1 pmu_init_v1;
struct pmu_init_msg_pmu_v0 pmu_init_v0;
struct pmu_init_msg_pmu_v2 pmu_init_v2;
struct pmu_init_msg_pmu_v3 pmu_init_v3; struct pmu_init_msg_pmu_v3 pmu_init_v3;
struct pmu_init_msg_pmu_v4 pmu_init_v4; struct pmu_init_msg_pmu_v4 pmu_init_v4;
}; };