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gpu: nvgpu: unit: ce: switch to gops

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Change the unit test to use gops instead of the HALs directly.
Update the Targets SWUTS keyword to reflect the change.

This allows linkage to test coverage in the SWUD.

JIRA NVGPU-4818

Change-Id: Ib87b4cdb68112eda89ba8844677b46c67b5e6745
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279484
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2020-01-14 21:02:04 -05:00
committed by Alex Waterman
parent 12df00c943
commit 9fc6bf3a4b
2 changed files with 32 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
userspace/units/ce/nvgpu-ce.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -180,12 +180,13 @@ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args)
int inst_id;
u32 intr_val;
g->ops.ce.isr_stall = gv11b_ce_stall_isr;
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
intr_status_written[inst_id] = 0;
intr_val = 0x1f; /* all intr sources */
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
gv11b_ce_stall_isr(g, inst_id, 0);
g->ops.ce.isr_stall(g, inst_id, 0);
if (intr_status_written[inst_id] != (intr_val &
~ce_intr_status_nonblockpipe_pending_f())) {
ret = UNIT_FAIL;
@@ -198,7 +199,7 @@ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args)
intr_val = 0x0;
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
gv11b_ce_stall_isr(g, inst_id, 0);
g->ops.ce.isr_stall(g, inst_id, 0);
if (intr_status_written[inst_id] != intr_val) {
ret = UNIT_FAIL;
unit_err(m, "intr_status not cleared, only 0x%08x\n",
@@ -218,12 +219,13 @@ int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args)
u32 intr_val;
u32 val;
g->ops.ce.isr_nonstall = gp10b_ce_nonstall_isr;
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
intr_status_written[inst_id] = 0;
intr_val = 0x1f; /* all intr sources */
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
val = gp10b_ce_nonstall_isr(g, inst_id, 0);
val = g->ops.ce.isr_nonstall(g, inst_id, 0);
if (val != (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_NONSTALL_OPS_POST_EVENTS)) {
ret = UNIT_FAIL;
@@ -242,7 +244,7 @@ int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args)
intr_val = 0x0;
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
val = gp10b_ce_nonstall_isr(g, inst_id, 0);
val = g->ops.ce.isr_nonstall(g, inst_id, 0);
if (val != 0U) {
ret = UNIT_FAIL;
unit_err(m, "incorrect ops returned 0x%08x\n", val);
@@ -272,6 +274,8 @@ int test_mthd_buffer_fault_in_bar2_fault(struct unit_module *m, struct gk20a *g,
int inst_id;
u32 intr_val;
g->ops.ce.mthd_buffer_fault_in_bar2_fault =
gv11b_ce_mthd_buffer_fault_in_bar2_fault;
g->ops.top.get_num_lce = mock_get_num_lce;
intr_val = 0x1f; /* all intr sources */
@@ -280,7 +284,7 @@ int test_mthd_buffer_fault_in_bar2_fault(struct unit_module *m, struct gk20a *g,
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
}
gv11b_ce_mthd_buffer_fault_in_bar2_fault(g);
g->ops.ce.mthd_buffer_fault_in_bar2_fault(g);
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
if (intr_status_written[inst_id] !=
ce_intr_status_mthd_buffer_fault_pending_f()) {
@@ -297,7 +301,7 @@ int test_mthd_buffer_fault_in_bar2_fault(struct unit_module *m, struct gk20a *g,
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
}
gv11b_ce_mthd_buffer_fault_in_bar2_fault(g);
g->ops.ce.mthd_buffer_fault_in_bar2_fault(g);
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
if (intr_status_written[inst_id] != 0) {
ret = UNIT_FAIL;
@@ -316,10 +320,11 @@ int test_get_num_pce(struct unit_module *m, struct gk20a *g, void *args)
u32 pce_map_val; /* 16 bit bitmap */
u32 val;
g->ops.ce.get_num_pce = gv11b_ce_get_num_pce;
for (pce_map_val = 0; pce_map_val <= U16_MAX; pce_map_val++) {
nvgpu_posix_io_writel_reg_space(g, ce_pce_map_r(),
pce_map_val);
val = gv11b_ce_get_num_pce(g);
val = g->ops.ce.get_num_pce(g);
if (val != hweight32(pce_map_val)) {
unit_return_fail(m, "incorrect value %u\n", val);
}
@@ -333,11 +338,12 @@ int test_init_prod_values(struct unit_module *m, struct gk20a *g, void *args)
int inst_id;
u32 val;
g->ops.ce.init_prod_values = gv11b_ce_init_prod_values;
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
/* init reg to known state */
nvgpu_posix_io_writel_reg_space(g, ce_lce_opt_r(inst_id), 0U);
}
gv11b_ce_init_prod_values(g);
g->ops.ce.init_prod_values(g);
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
/* verify written correctly */
val = nvgpu_posix_io_readl_reg_space(g, ce_lce_opt_r(inst_id));

33
userspace/units/ce/nvgpu-ce.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -75,7 +75,7 @@ int test_free_env(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: nvgpu_ce_init_support
* Targets: gops_ce.ce_init_support, nvgpu_ce_init_support
*
* Input: test_setup_env must have been run.
*
@@ -97,18 +97,18 @@ int test_ce_init_support(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: gv11b_ce_stall_isr
* Targets: gops_ce.isr_stall, gv11b_ce_stall_isr
*
* Input: test_setup_env must have been run.
*
* Steps:
* - Set all CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gv11b_ce_stall_isr.
* - Call gops_ce.isr_stall.
* - Verify all (and only) the stall interrupts are cleared.
* - Set no CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gv11b_ce_stall_isr.
* - Call gops_ce.isr_stall.
* - Verify no interrupts are cleared.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
@@ -122,19 +122,19 @@ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: gp10b_ce_nonstall_isr
* Targets: gops_ce.isr_nonstall, gp10b_ce_nonstall_isr
*
* Input: test_setup_env must have been run.
*
* Steps:
* - Set all CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gp10b_ce_nonstall_isr.
* - Call gops_ce.isr_nonstall.
* - Verify only the nonstall interrupt is cleared and the expected ops are
* returned.
* - Set no CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gp10b_ce_nonstall_isr.
* - Call gops_ce.isr_nonstall.
* - Verify no interrupts are cleared and no ops are returned.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
@@ -148,18 +148,19 @@ int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: gv11b_ce_mthd_buffer_fault_in_bar2_fault
* Targets: gops_ce.mthd_buffer_fault_in_bar2_fault,
* gv11b_ce_mthd_buffer_fault_in_bar2_fault
*
* Input: test_setup_env must have been run.
*
* Steps:
* - Set all CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gv11b_ce_mthd_buffer_fault_in_bar2_fault.
* - Call gops_ce.mthd_buffer_fault_in_bar2_fault.
* - Verify only the correct interrupt is cleared.
* - Set no CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gv11b_ce_mthd_buffer_fault_in_bar2_fault.
* - Call gops_ce.mthd_buffer_fault_in_bar2_fault.
* - Verify no interrupts are cleared.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
@@ -170,18 +171,18 @@ int test_mthd_buffer_fault_in_bar2_fault(struct unit_module *m, struct gk20a *g,
/**
* Test specification for: test_get_num_pce
*
* Description: Validate function of gv11b_ce_get_num_pce.
* Description: Validate function of gops_ce.get_num_pce.
*
* Test Type: Feature
*
* Targets: gv11b_ce_get_num_pce
* Targets: gops_ce.get_num_pce, gv11b_ce_get_num_pce
*
* Input: test_setup_env must have been run.
*
* Steps:
* - Loop through all possible 16 bit values for the PCE Map register.
* - For each value, write to the PCE Map register.
* - Call gv11b_ce_get_num_pce and verify the correct number of PCEs is
* - Call gops_ce.get_num_pce and verify the correct number of PCEs is
* returned.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
@@ -195,13 +196,13 @@ int test_get_num_pce(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: gv11b_ce_init_prod_values
* Targets: gops_ce.init_prod_values, gv11b_ce_init_prod_values
*
* Input: test_setup_env must have been run.
*
* Steps:
* - Clear the LCE Options register for all instances.
* - Call gv11b_ce_init_prod_values.
* - Call gops_ce.init_prod_values.
* - Verify all instances of the LCE Options register are set properly.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.