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Open source GPL/LGPL release
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svcmobrel-release
220
drivers/gpu/nvgpu/common/fifo/preempt.c
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220
drivers/gpu/nvgpu/common/fifo/preempt.c
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/*
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* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/soc.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/errata.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/types.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/preempt.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/cic.h>
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#include <nvgpu/rc.h>
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#ifdef CONFIG_NVGPU_LS_PMU
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#include <nvgpu/pmu/mutex.h>
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#endif
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u32 nvgpu_preempt_get_timeout(struct gk20a *g)
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{
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return g->ctxsw_timeout_period_ms;
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}
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int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg)
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{
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int ret = 0;
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u32 preempt_retry_count = 10U;
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u32 preempt_retry_timeout =
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nvgpu_preempt_get_timeout(g) / preempt_retry_count;
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#ifdef CONFIG_NVGPU_LS_PMU
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u32 token = PMU_INVALID_MUTEX_OWNER_ID;
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int mutex_ret = 0;
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#endif
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nvgpu_log_fn(g, "tsgid: %d", tsg->tsgid);
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if (tsg->runlist == NULL) {
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return 0;
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}
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do {
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nvgpu_mutex_acquire(&tsg->runlist->runlist_lock);
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if (nvgpu_is_errata_present(g, NVGPU_ERRATA_2016608)) {
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nvgpu_runlist_set_state(g, BIT32(tsg->runlist->id),
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RUNLIST_DISABLED);
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}
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#ifdef CONFIG_NVGPU_LS_PMU
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mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu,
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PMU_MUTEX_ID_FIFO, &token);
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#endif
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g->ops.fifo.preempt_trigger(g, tsg->tsgid, ID_TYPE_TSG);
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/*
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* Poll for preempt done. if stalling interrupts are pending
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* while preempt is in progress we poll for stalling interrupts
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* to finish based on return value from this function and
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* retry preempt again.
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* If HW is hung, on the last retry instance we try to identify
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* the engines hung and set the runlist reset_eng_bitmask
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* and mark preemption completion.
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*/
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ret = g->ops.fifo.is_preempt_pending(g, tsg->tsgid,
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ID_TYPE_TSG, preempt_retry_count > 1U);
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#ifdef CONFIG_NVGPU_LS_PMU
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if (mutex_ret == 0) {
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int err = nvgpu_pmu_lock_release(g, g->pmu,
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PMU_MUTEX_ID_FIFO, &token);
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if (err != 0) {
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nvgpu_err(g, "PMU_MUTEX_ID_FIFO not released err=%d", err);
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}
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}
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#endif
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if (nvgpu_is_errata_present(g, NVGPU_ERRATA_2016608)) {
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nvgpu_runlist_set_state(g, BIT32(tsg->runlist->id),
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RUNLIST_ENABLED);
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}
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nvgpu_mutex_release(&tsg->runlist->runlist_lock);
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if (ret != -EAGAIN) {
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break;
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}
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ret = nvgpu_cic_wait_for_stall_interrupts(g, preempt_retry_timeout);
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if (ret != 0) {
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nvgpu_log_info(g, "wait for stall interrupts failed %d", ret);
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}
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} while (--preempt_retry_count != 0U);
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if (ret != 0) {
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if (nvgpu_platform_is_silicon(g)) {
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nvgpu_err(g, "preempt timed out for tsgid: %u, "
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"ctxsw timeout will trigger recovery if needed",
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tsg->tsgid);
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} else {
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nvgpu_rc_preempt_timeout(g, tsg);
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}
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}
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return ret;
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}
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int nvgpu_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch)
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{
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int err;
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struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
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if (tsg != NULL) {
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err = g->ops.fifo.preempt_tsg(ch->g, tsg);
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} else {
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err = g->ops.fifo.preempt_channel(ch->g, ch);
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}
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return err;
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}
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/* called from rc */
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int nvgpu_preempt_poll_tsg_on_pbdma(struct gk20a *g,
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struct nvgpu_tsg *tsg)
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{
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unsigned long runlist_served_pbdmas;
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unsigned long pbdma_id_bit;
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u32 tsgid, pbdma_id;
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if (g->ops.fifo.preempt_poll_pbdma == NULL) {
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return 0;
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}
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tsgid = tsg->tsgid;
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runlist_served_pbdmas = tsg->runlist->pbdma_bitmask;
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for_each_set_bit(pbdma_id_bit, &runlist_served_pbdmas,
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nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA)) {
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pbdma_id = U32(pbdma_id_bit);
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/*
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* If pbdma preempt fails the only option is to reset
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* GPU. Any sort of hang indicates the entire GPU’s
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* memory system would be blocked.
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*/
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if (g->ops.fifo.preempt_poll_pbdma(g, tsgid, pbdma_id) != 0) {
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nvgpu_err(g, "PBDMA preempt failed");
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return -EBUSY;
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}
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}
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return 0;
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}
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/*
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* This should be called with runlist_lock held for all the
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* runlists set in runlists_mask
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*/
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void nvgpu_fifo_preempt_runlists_for_rc(struct gk20a *g, u32 runlists_bitmask)
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{
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struct nvgpu_fifo *f = &g->fifo;
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u32 i;
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#ifdef CONFIG_NVGPU_LS_PMU
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u32 token = PMU_INVALID_MUTEX_OWNER_ID;
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int mutex_ret = 0;
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#endif
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/* runlist_lock are locked by teardown and sched are disabled too */
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nvgpu_log_fn(g, "preempt runlists_bitmask:0x%08x", runlists_bitmask);
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#ifdef CONFIG_NVGPU_LS_PMU
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mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu,
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PMU_MUTEX_ID_FIFO, &token);
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#endif
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for (i = 0U; i < f->num_runlists; i++) {
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struct nvgpu_runlist *runlist;
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runlist = &f->active_runlists[i];
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if ((BIT32(runlist->id) & runlists_bitmask) == 0U) {
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continue;
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}
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/* issue runlist preempt */
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g->ops.fifo.preempt_trigger(g, runlist->id,
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ID_TYPE_RUNLIST);
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#ifdef CONFIG_NVGPU_RECOVERY
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/*
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* Preemption will never complete in RC due to some
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* fatal condition. Do not poll for preemption to
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* complete. Reset engines served by runlists.
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*/
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runlist->reset_eng_bitmask = runlist->eng_bitmask;
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#endif
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}
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#ifdef CONFIG_NVGPU_LS_PMU
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if (mutex_ret == 0) {
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int err = nvgpu_pmu_lock_release(g, g->pmu, PMU_MUTEX_ID_FIFO,
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&token);
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if (err != 0) {
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nvgpu_err(g, "PMU_MUTEX_ID_FIFO not released err=%d",
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err);
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}
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}
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#endif
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}
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