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git://nv-tegra.nvidia.com/linux-nvgpu.git
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Open source GPL/LGPL release
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svcmobrel-release
196
drivers/gpu/nvgpu/common/gr/fs_state.c
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196
drivers/gpu/nvgpu/common/gr/fs_state.c
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/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/gr/config.h>
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#include <nvgpu/gr/fs_state.h>
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#include <nvgpu/gr/gr_instances.h>
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#include <nvgpu/grmgr.h>
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static int gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config)
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{
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int err;
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u32 *tpc_sm_id;
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u32 sm_id_size = g->ops.gr.init.get_sm_id_size();
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
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tpc_sm_id = nvgpu_kcalloc(g, sm_id_size, sizeof(u32));
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if (tpc_sm_id == NULL) {
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return -ENOMEM;
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}
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err = g->ops.gr.init.sm_id_config(g, tpc_sm_id, config, NULL, false);
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nvgpu_kfree(g, tpc_sm_id);
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, "done");
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return err;
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}
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static void gr_load_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config)
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{
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u32 pes_tpc_mask = 0;
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u32 gpc, pes;
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u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
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GPU_LIT_NUM_TPC_PER_GPC);
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 max_tpc_count = nvgpu_gr_config_get_max_tpc_count(config);
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u32 fuse_tpc_mask;
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u32 val;
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u32 cur_gr_instance = nvgpu_gr_get_cur_instance_id(g);
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u32 gpc_phys_id;
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#endif
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/* gv11b has 1 GPC and 4 TPC/GPC, so mask will not overflow u32 */
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for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(config); gpc++) {
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for (pes = 0;
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pes < nvgpu_gr_config_get_pe_count_per_gpc(config);
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pes++) {
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pes_tpc_mask |= nvgpu_gr_config_get_pes_tpc_mask(
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config, gpc, pes) <<
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nvgpu_safe_mult_u32(num_tpc_per_gpc, gpc);
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}
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}
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nvgpu_log_info(g, "pes_tpc_mask %u\n", pes_tpc_mask);
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#ifdef CONFIG_NVGPU_NON_FUSA
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
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/*
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* Fuse registers must be queried with physical gpc-id and not
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* the logical ones. For tu104 and before chips logical gpc-id
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* is same as physical gpc-id for non-floorswept config but for
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* chips after tu104 it may not be true.
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*/
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gpc_phys_id = nvgpu_grmgr_get_gr_gpc_phys_id(g,
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cur_gr_instance, 0U);
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fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, gpc_phys_id);
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if ((g->tpc_fs_mask_user != 0U) &&
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(g->tpc_fs_mask_user != fuse_tpc_mask)) {
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if (fuse_tpc_mask == nvgpu_safe_sub_u32(BIT32(max_tpc_count),
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U32(1))) {
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val = g->tpc_fs_mask_user;
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val &= nvgpu_safe_sub_u32(BIT32(max_tpc_count), U32(1));
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/*
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* skip tpc to disable the other tpc cause channel
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* timeout
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*/
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val = nvgpu_safe_sub_u32(BIT32(hweight32(val)), U32(1));
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pes_tpc_mask = val;
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}
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}
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}
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#endif
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g->ops.gr.init.tpc_mask(g, 0, pes_tpc_mask);
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}
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int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
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{
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u32 tpc_index, gpc_index;
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u32 sm_id = 0;
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 fuse_tpc_mask;
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u32 max_tpc_cnt;
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u32 cur_gr_instance = nvgpu_gr_get_cur_instance_id(g);
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u32 gpc_phys_id;
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#endif
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u32 gpc_cnt, tpc_cnt;
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u32 num_sm;
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int err = 0;
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
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g->ops.gr.init.fs_state(g);
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err = g->ops.gr.config.init_sm_id_table(g, config);
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if (err != 0) {
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return err;
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}
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num_sm = nvgpu_gr_config_get_no_of_sm(config);
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nvgpu_assert(num_sm > 0U);
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for (sm_id = 0; sm_id < num_sm; sm_id++) {
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struct nvgpu_sm_info *sm_info =
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nvgpu_gr_config_get_sm_info(config, sm_id);
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tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
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gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
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g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id,
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config, NULL, false);
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}
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
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g->ops.gr.init.pd_tpc_per_gpc(g, config);
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}
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#ifdef CONFIG_NVGPU_GRAPHICS
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
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/* gr__setup_pd_mapping */
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g->ops.gr.init.rop_mapping(g, config);
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g->ops.gr.init.pd_skip_table_gpc(g, config);
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}
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#endif
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gpc_cnt = nvgpu_gr_config_get_gpc_count(config);
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tpc_cnt = nvgpu_gr_config_get_tpc_count(config);
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#ifdef CONFIG_NVGPU_NON_FUSA
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
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/*
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* Fuse registers must be queried with physical gpc-id and not
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* the logical ones. For tu104 and before chips logical gpc-id
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* is same as physical gpc-id for non-floorswept config but for
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* chips after tu104 it may not be true.
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*/
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gpc_phys_id = nvgpu_grmgr_get_gr_gpc_phys_id(g,
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cur_gr_instance, 0U);
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fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, gpc_phys_id);
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max_tpc_cnt = nvgpu_gr_config_get_max_tpc_count(config);
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if ((g->tpc_fs_mask_user != 0U) &&
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(fuse_tpc_mask ==
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nvgpu_safe_sub_u32(BIT32(max_tpc_cnt), U32(1)))) {
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u32 val = g->tpc_fs_mask_user;
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val &= nvgpu_safe_sub_u32(BIT32(max_tpc_cnt), U32(1));
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tpc_cnt = (u32)hweight32(val);
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}
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}
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#endif
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g->ops.gr.init.cwd_gpcs_tpcs_num(g, gpc_cnt, tpc_cnt);
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gr_load_tpc_mask(g, config);
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err = gr_load_sm_id_config(g, config);
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if (err != 0) {
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nvgpu_err(g, "load_smid_config failed err=%d", err);
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}
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, "done");
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return err;
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}
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