nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

Open source GPL/LGPL release

Browse Source
This commit is contained in:
svcmobrel-release
2025-12-19 15:25:44 -08:00
commit 9fc87a7ec7
2261 changed files with 576825 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
userspace/units/falcon/Makefile Normal file
View File

@@ -0,0 +1,27 @@
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
.SUFFIXES:
OBJS = falcon_utf.o
MODULE = falcon_utf
include ../Makefile.units

29
userspace/units/falcon/Makefile.interface.tmk Normal file
View File

@@ -0,0 +1,29 @@
################################### tell Emacs this is a -*- makefile-gmake -*-
#
# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved.
#
# NVIDIA CORPORATION and its licensors retain all intellectual property
# and proprietary rights in and to this software, related documentation
# and any modifications thereto. Any use, reproduction, disclosure or
# distribution of this software and related documentation without an express
# license agreement from NVIDIA CORPORATION is strictly prohibited.
#
# tmake for SW Mobile component makefile
#
# libfalcon_utf interface makefile fragment
#
###############################################################################
ifdef NV_INTERFACE_FLAG_SHARED_LIBRARY_SECTION
NV_INTERFACE_NAME := falcon_utf
NV_INTERFACE_EXPORTS := lib$(NV_INTERFACE_NAME)
NV_INTERFACE_SONAME := lib$(NV_INTERFACE_NAME).so
endif
# Local Variables:
# indent-tabs-mode: t
# tab-width: 8
# End:
# vi: set tabstop=8 noexpandtab:

26
userspace/units/falcon/Makefile.tmk Normal file
View File

@@ -0,0 +1,26 @@
################################### tell Emacs this is a -*- makefile-gmake -*-
#
# Copyright (c) 2019 NVIDIA CORPORATION. All Rights Reserved.
#
# NVIDIA CORPORATION and its licensors retain all intellectual property
# and proprietary rights in and to this software, related documentation
# and any modifications thereto. Any use, reproduction, disclosure or
# distribution of this software and related documentation without an express
# license agreement from NVIDIA CORPORATION is strictly prohibited.
#
# tmake for SW Mobile component makefile
#
# Component makefile for compiling falcon_utf common tests.
#
###############################################################################
NVGPU_UNIT_NAME = falcon_utf
NVGPU_UNIT_SRCS = falcon_utf.c
include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
# Local Variables:
# indent-tabs-mode: t
# tab-width: 8
# End:
# vi: set tabstop=8 noexpandtab:

33
userspace/units/falcon/falcon_tests/Makefile Normal file
View File

@@ -0,0 +1,33 @@
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
.SUFFIXES:
OBJS = falcon.o
MODULE = falcon
LIB_PATHS += -lfalcon_utf
include ../../Makefile.units
lib$(MODULE).so: falcon_utf
falcon_utf:
$(MAKE) -C ..

23
userspace/units/falcon/falcon_tests/Makefile.interface.tmk Normal file
View File

@@ -0,0 +1,23 @@
################################### tell Emacs this is a -*- makefile-gmake -*-
#
# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved.
#
# NVIDIA CORPORATION and its licensors retain all intellectual property
# and proprietary rights in and to this software, related documentation
# and any modifications thereto. Any use, reproduction, disclosure or
# distribution of this software and related documentation without an express
# license agreement from NVIDIA CORPORATION is strictly prohibited.
#
# tmake for SW Mobile component makefile
#
###############################################################################
NVGPU_UNIT_NAME=falcon
include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
# Local Variables:
# indent-tabs-mode: t
# tab-width: 8
# End:
# vi: set tabstop=8 noexpandtab:

27
userspace/units/falcon/falcon_tests/Makefile.tmk Normal file
View File

@@ -0,0 +1,27 @@
################################### tell Emacs this is a -*- makefile-gmake -*-
#
# Copyright (c) 2019-2020 NVIDIA CORPORATION. All Rights Reserved.
#
# NVIDIA CORPORATION and its licensors retain all intellectual property
# and proprietary rights in and to this software, related documentation
# and any modifications thereto. Any use, reproduction, disclosure or
# distribution of this software and related documentation without an express
# license agreement from NVIDIA CORPORATION is strictly prohibited.
#
# tmake for SW Mobile component makefile
#
###############################################################################
NVGPU_UNIT_NAME=falcon
NVGPU_UNIT_SRCS=falcon.c
NVGPU_UNIT_INTERFACE_DIRS := \
$(NV_COMPONENT_DIR)/..
include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
# Local Variables:
# indent-tabs-mode: t
# tab-width: 8
# End:
# vi: set tabstop=8 noexpandtab:

1409
userspace/units/falcon/falcon_tests/falcon.c Normal file
View File

File diff suppressed because it is too large Load Diff

514
userspace/units/falcon/falcon_tests/nvgpu-falcon.h Normal file
View File

@@ -0,0 +1,514 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
struct gk20a;
struct unit_module;
/** @addtogroup SWUTS-falcon
* @{
*
* Software Unit Test Specification for falcon
*/
/**
* Test specification for: test_falcon_sw_init_free
*
* Description: The falcon unit shall be able to initialize the falcon's
* base register address, required software setup for valid falcon ID.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_get_instance, nvgpu_falcon_sw_init,
* nvgpu_falcon_sw_free, gops_pmu.falcon_base_addr,
* gv11b_pmu_falcon_base_addr, gops_pmu.setup_apertures,
* gv11b_setup_apertures, gops_pmu.flcn_setup_boot_config,
* gv11b_pmu_flcn_setup_boot_config
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_sw_init with valid falcon ID before initializing HAL.
* - Verify that falcon initialization fails since valid gpu_arch|impl
* are not initialized.
* - Invoke nvgpu_falcon_sw_free with above falcon ID.
* - Initialize the test environment:
* - Register read/write IO callbacks that handle falcon IO as well.
* - Add relevant fuse registers to the register space.
* - Initialize hal to setup the hal functions.
* - Initialize UTF (Unit Test Framework) falcon structures for PMU and
* GPCCS falcons.
* - Create and initialize test buffer with random data.
* - Invoke nvgpu_falcon_sw_init with invalid falcon ID.
* - Verify that falcon initialization fails.
* - Invoke nvgpu_falcon_sw_free with above falcon ID.
* - Invoke nvgpu_falcon_sw_init with valid falcon ID.
* - Verify that falcon initialization succeeds.
* - Invoke nvgpu_falcon_sw_free with above falcon ID.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_sw_init_free(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_get_id
*
* Description: The falcon unit shall be able to return the falcon ID
* for the falcon.
*
* Test Type: Feature
*
* Targets: nvgpu_falcon_get_id
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_get_id with the gpccs falcon struct.
* - Verify that return falcon ID is #FALCON_ID_GPCCS.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_get_id(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_reset
*
* Description: The falcon unit shall be able to reset the falcon CPU or trigger
* engine specific reset for valid falcon ID.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_reset, gops_falcon.reset, gk20a_falcon_reset
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_reset with NULL falcon pointer.
* - Verify that reset fails with -EINVAL return value.
* - Invoke nvgpu_falcon_reset with uninitialized falcon struct.
* - Verify that reset fails with -EINVAL return value.
* - Invoke nvgpu_falcon_reset with valid falcon ID.
* - Verify that falcon initialization succeeds and check that bit
* falcon_cpuctl_hreset_f is set in falcon_cpuctl register.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_reset(struct unit_module *m, struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_mem_scrub
*
* Description: The falcon unit shall be able to check and return the falcon
* memory scrub status.
*
* Test Type: Feature, Error guessing, Error injection
*
* Targets: nvgpu_falcon_mem_scrub_wait, gops_falcon.is_falcon_scrubbing_done,
* gk20a_is_falcon_scrubbing_done
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_mem_scrub_wait with uninitialized falcon struct.
* - Verify that wait fails with -EINVAL return value.
* - Invoke nvgpu_falcon_mem_scrub_wait with initialized falcon struct where
* underlying falcon's memory scrub is completed.
* - Verify that wait succeeds with 0 return value.
* - Invoke nvgpu_falcon_mem_scrub_wait with initialized falcon struct where
* underlying falcon's memory scrub is yet to complete.
* - Verify that wait fails with -ETIMEDOUT return value.
* - Enable fault injection for the timer init call for branch coverage.
* - Verify that wait fails with -ETIMEDOUT return value.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_scrub(struct unit_module *m, struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_idle
*
* Description: The falcon unit shall be able to check and return the falcon
* idle status.
*
* Test Type: Feature, Error guessing, Error injection
*
* Input: None.
*
* Targets: nvgpu_falcon_wait_idle, gops_falcon.is_falcon_idle,
* gk20a_is_falcon_idle
*
* Steps:
* - Invoke nvgpu_falcon_wait_idle with uninitialized falcon struct.
* - Verify that wait fails with -EINVAL return value.
* - Invoke nvgpu_falcon_wait_idle with initialized falcon struct where
* underlying falcon is idle.
* - Verify that wait succeeds with 0 return value.
* - Invoke nvgpu_falcon_wait_idle with initialized falcon struct where
* underlying falcon's ext units are busy but falcon CPU is idle.
* - Verify that wait fails with -ETIMEDOUT return value.
* - Invoke nvgpu_falcon_wait_idle with initialized falcon struct where
* underlying falcon is not idle.
* - Verify that wait fails with -ETIMEDOUT return value.
* - Enable fault injection for the timer init call for branch coverage.
* - Verify that wait fails with -ETIMEDOUT return value.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_idle(struct unit_module *m, struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_halt
*
* Description: The falcon unit shall be able to check and return the falcon
* halt status.
*
* Test Type: Feature, Error guessing, Error injection
*
* Targets: nvgpu_falcon_wait_for_halt, gops_falcon.is_falcon_cpu_halted,
* gk20a_is_falcon_cpu_halted
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_wait_for_halt with uninitialized falcon struct.
* - Verify that wait fails with -EINVAL return value.
* - Invoke nvgpu_falcon_wait_for_halt with initialized falcon struct where
* underlying falcon is halted.
* - Verify that wait succeeds with 0 return value.
* - Invoke nvgpu_falcon_wait_for_halt with initialized falcon struct where
* underlying falcon is not halted.
* - Verify that wait fails with -ETIMEDOUT return value.
* - Enable fault injection for the timer init call for branch coverage.
* - Verify that wait fails with -ETIMEDOUT return value.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_halt(struct unit_module *m, struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_mem_rw_init
*
* Description: The falcon unit shall be able to write to falcon's IMEM and
* DMEM.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_copy_to_imem, nvgpu_falcon_copy_to_dmem,
* gops_falcon.copy_to_imem, gops_falcon.copy_to_dmem,
* gk20a_falcon_copy_to_imem, gk20a_falcon_copy_to_dmem
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* uninitialized falcon struct with sample random data.
* - Verify that writes fail with -EINVAL return value in both cases.
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data.
* - Verify that writes succeed with 0 return value in both cases.
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data of size that is
* not multiple of words.
* - Verify that writes succeed with 0 return value in both cases.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_init(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_mem_rw_range
*
* Description: The falcon unit shall be able to write to falcon's IMEM and
* DMEM in accessible range.
*
* Test Type: Feature, Boundary values
*
* Targets: nvgpu_falcon_copy_to_imem, nvgpu_falcon_copy_to_dmem,
* gops_falcon.copy_to_imem, gops_falcon.copy_to_dmem,
* gops_falcon.get_mem_size, gk20a_falcon_copy_to_imem,
* gk20a_falcon_copy_to_dmem, gk20a_falcon_get_mem_size
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data and valid range.
* - Verify that writes succeed with 0 return value in both cases.
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data and invalid range
* with valid and invalid offset.
* - Verify that writes fail with -EINVAL return value in both cases.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_range(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_mem_rw_fault
*
* Description: The falcon unit shall fail the call to copy to DMEM when
* DMEMC reads return invalid value due to HW fault.
*
* Test Type: Error injection
*
* Targets: nvgpu_falcon_copy_to_dmem, gops_falcon.copy_to_dmem,
* gk20a_falcon_copy_to_dmem
*
* Input: None.
*
* Steps:
* - Enable the falcon DMEMC read fault.
* - Invoke nvgpu_falcon_copy_to_dmem with initialized falcon struct with
* sample random data and valid range.
* - Disable the falcon DMEMC read fault.
* - Verify that writes failed.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_fault(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_mem_rw_aligned
*
* Description: The falcon unit shall be able to write to falcon's IMEM and
* DMEM only at aligned offsets.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_copy_to_imem, nvgpu_falcon_copy_to_dmem,
* gops_falcon.copy_to_imem, gops_falcon.copy_to_dmem,
* gk20a_falcon_copy_to_imem, gk20a_falcon_copy_to_dmem
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data and 4-byte aligned
* offset.
* - Verify that writes succeed with 0 return value in both cases.
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data and non 4-byte
* aligned offset.
* - Verify that writes fail with -EINVAL return value in both cases.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_aligned(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_mem_rw_zero
*
* Description: The falcon unit shall fail the API call to write zero
* bytes to falcon memory.
*
* Test Type: Error guessing
*
* Targets: nvgpu_falcon_copy_to_imem, nvgpu_falcon_copy_to_dmem,
* gops_falcon.copy_to_imem, gops_falcon.copy_to_dmem,
* gk20a_falcon_copy_to_imem, gk20a_falcon_copy_to_dmem
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with sample random data and zero bytes.
* - Verify that writes fail with -EINVAL return value in both cases.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_zero(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_mailbox
*
* Description: The falcon unit shall read and write value of falcon's mailbox
* registers.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_mailbox_read, nvgpu_falcon_mailbox_write,
* gops_falcon.mailbox_read, gops_falcon.mailbox_write,
* gk20a_falcon_mailbox_read, gk20a_falcon_mailbox_write
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_mailbox_read and nvgpu_falcon_mailbox_write with
* uninitialized falcon struct.
* - Verify that read returns zero.
* - Write a sample value to mailbox registers and read using the nvgpu APIs.
* - Verify the value by reading the registers through IO accessor.
* - Read/Write value from invalid mailbox register of initialized falcon.
* - Verify that read returns zero.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mailbox(struct unit_module *m, struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_bootstrap
*
* Description: The falcon unit shall configure the bootstrap parameters into
* falcon memory and registers.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_hs_ucode_load_bootstrap, gops_falcon.bootstrap,
* gk20a_falcon_bootstrap
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with uninitialized
* falcon struct.
* - Verify that call fails with -EINVAL return value.
* - Fetch the ACR firmware from filesystem.
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with initialized falcon struct.
* Fail the falcon reset by failing mem scrub wait.
* - Verify that bootstrap fails.
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with initialized falcon struct.
* Fail the imem copy for non-secure code by setting invalid size in ucode
* header.
* - Verify that bootstrap fails.
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with initialized falcon struct.
* Fail the imem copy for secure code by setting invalid size in ucode header.
* - Verify that bootstrap fails.
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with initialized falcon struct.
* Fail the imem copy for secure code by setting invalid size in ucode header.
* - Verify that bootstrap fails.
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with initialized falcon struct.
* Fail the dmem copy setting invalid dmem size in ucode header.
* - Verify that bootstrap fails.
* - Invoke nvgpu_falcon_hs_ucode_load_bootstrap with initialized falcon struct.
* - Verify that bootstrap succeeds and verify the expected state of registers
* falcon_dmactl_r, falcon_falcon_bootvec_r, falcon_falcon_cpuctl_r.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_bootstrap(struct unit_module *m, struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_mem_rw_unaligned_cpu_buffer
*
* Description: The falcon unit shall be able to read/write from/to falcon's
* IMEM and DMEM from memory buffer that is unaligned.
*
* Test Type: Feature
*
* Targets: nvgpu_falcon_copy_to_imem, nvgpu_falcon_copy_to_dmem,
* gops_falcon.copy_to_imem, gops_falcon.copy_to_dmem,
* gk20a_falcon_copy_to_imem, gk20a_falcon_copy_to_dmem
*
* Input: None.
*
* Steps:
* - Initialize unaligned random data memory buffer and set size.
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_to_dmem with
* initialized falcon struct with above initialized sample random data
* and valid range.
* - Verify that writes succeed with 0 return value in both cases.
* - Write data of size 1K to valid range in imem/dmem from unaligned data
* to verify the buffering logic and cover branches in
* falcon_copy_to_dmem|imem_unaligned_src.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_unaligned_cpu_buffer(struct unit_module *m,
struct gk20a *g, void *__args);
/**
* Test specification for: test_falcon_mem_rw_inval_port
*
* Description: The falcon unit shall not be able to read/write from/to falcon's
* memory from invalid port.
*
* Test Type: Error guessing
*
* Targets: nvgpu_falcon_copy_to_imem, gops_falcon.copy_to_imem,
* gops_falcon.get_ports_count, gk20a_falcon_copy_to_imem,
* gk20a_falcon_get_ports_count
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_copy_to_imem and nvgpu_falcon_copy_from_imem with
* initialized falcon struct with initialized sample random data, valid
* range but invalid port.
* - Verify that return value is -EINVAL.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_mem_rw_inval_port(struct unit_module *m, struct gk20a *g,
void *__args);
/**
* Test specification for: test_falcon_irq
*
* Description: The falcon unit shall be able to set or clear the falcon irq
* mask and destination registers for supported falcons.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_falcon_set_irq, gops_falcon.set_irq,
* gk20a_falcon_set_irq
*
* Input: None.
*
* Steps:
* - Invoke nvgpu_falcon_set_irq with uninitialized falcon struct.
* - Invoke nvgpu_falcon_set_irq with initialized falcon struct where
* underlying falcon has interrupt support disabled.
* - Invoke nvgpu_falcon_set_irq to enable the interrupts with
* initialized falcon struct and sample interrupt mask and
* destination values and the underlying falcon has
* interrupt support enabled.
* - Verify that falcon_irqmset_r and falcon_irqdest_r are set as
* expected.
* - Invoke nvgpu_falcon_set_irq to disable the interrupts with
* initialized falcon struct and the underlying falcon has
* interrupt support enabled.
* - Verify that falcon_irqmclr_r is set to 0xffffffff.
*
* Output: Returns PASS if the steps above were executed successfully. FAIL
* otherwise.
*/
int test_falcon_irq(struct unit_module *m, struct gk20a *g, void *__args);

255
userspace/units/falcon/falcon_utf.c Normal file
View File

@@ -0,0 +1,255 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <unit/io.h>
#include <nvgpu/falcon.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/kmem.h>
#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
#include "falcon_utf.h"
#include <nvgpu/posix/posix-fault-injection.h>
struct nvgpu_posix_fault_inj *nvgpu_utf_falcon_memcpy_get_fault_injection(void)
{
struct nvgpu_posix_fault_inj_container *c =
nvgpu_posix_fault_injection_get_container();
return &c->falcon_memcpy_fi;
}
void nvgpu_utf_falcon_writel_access_reg_fn(struct gk20a *g,
struct utf_falcon *flcn,
struct nvgpu_reg_access *access)
{
u32 addr_mask = falcon_falcon_dmemc_offs_m() |
falcon_falcon_dmemc_blk_m();
u32 flcn_base;
u32 ctrl_r;
u32 offset;
flcn_base = flcn->flcn->flcn_base;
if (access->addr == (flcn_base + falcon_falcon_imemd_r(0))) {
ctrl_r = nvgpu_posix_io_readl_reg_space(g,
flcn_base + falcon_falcon_imemc_r(0));
if (ctrl_r & falcon_falcon_imemc_aincw_f(1)) {
offset = ctrl_r & addr_mask;
*((u32 *) ((u8 *)flcn->imem + offset)) = access->value;
offset += 4U;
ctrl_r &= ~(addr_mask);
ctrl_r |= offset;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_imemc_r(0), ctrl_r);
}
} else if (access->addr == (flcn_base + falcon_falcon_dmemd_r(0))) {
ctrl_r = nvgpu_posix_io_readl_reg_space(g,
flcn_base + falcon_falcon_dmemc_r(0));
if (ctrl_r & falcon_falcon_dmemc_aincw_f(1)) {
offset = ctrl_r & addr_mask;
*((u32 *) ((u8 *)flcn->dmem + offset)) = access->value;
offset += 4U;
ctrl_r &= ~(addr_mask);
ctrl_r |= offset;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_dmemc_r(0), ctrl_r);
}
} else if (access->addr == (flcn_base + falcon_falcon_cpuctl_r())) {
if (access->value == falcon_falcon_cpuctl_halt_intr_m()) {
access->value = nvgpu_posix_io_readl_reg_space(g,
access->addr);
access->value |= falcon_falcon_cpuctl_halt_intr_m();
nvgpu_posix_io_writel_reg_space(g, access->addr,
access->value);
} else if (access->value == falcon_falcon_cpuctl_startcpu_f(1)) {
access->value = nvgpu_posix_io_readl_reg_space(g,
access->addr);
access->value |= falcon_falcon_cpuctl_startcpu_f(1);
nvgpu_posix_io_writel_reg_space(g, access->addr,
access->value);
/* set falcon mailbox0 to value 0 */
nvgpu_posix_io_writel_reg_space(g, flcn_base +
falcon_falcon_mailbox0_r(), 0);
}
}
nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
}
void nvgpu_utf_falcon_readl_access_reg_fn(struct gk20a *g,
struct utf_falcon *flcn,
struct nvgpu_reg_access *access)
{
u32 addr_mask = falcon_falcon_dmemc_offs_m() |
falcon_falcon_dmemc_blk_m();
u32 flcn_base;
u32 ctrl_r;
u32 offset;
flcn_base = flcn->flcn->flcn_base;
if (access->addr == (flcn_base + falcon_falcon_imemd_r(0))) {
ctrl_r = nvgpu_posix_io_readl_reg_space(g,
flcn_base + falcon_falcon_imemc_r(0));
if (ctrl_r & falcon_falcon_dmemc_aincr_f(1)) {
offset = ctrl_r & addr_mask;
access->value = *((u32 *) ((u8 *)flcn->imem + offset));
offset += 4U;
ctrl_r &= ~(addr_mask);
ctrl_r |= offset;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_imemc_r(0), ctrl_r);
}
} else if (access->addr == (flcn_base + falcon_falcon_dmemd_r(0))) {
ctrl_r = nvgpu_posix_io_readl_reg_space(g,
flcn_base + falcon_falcon_dmemc_r(0));
if (ctrl_r & falcon_falcon_dmemc_aincr_f(1)) {
offset = ctrl_r & addr_mask;
access->value = *((u32 *) ((u8 *)flcn->dmem + offset));
offset += 4U;
ctrl_r &= ~(addr_mask);
ctrl_r |= offset;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_dmemc_r(0), ctrl_r);
}
} else if (access->addr == (flcn_base + falcon_falcon_dmemc_r(0))) {
ctrl_r = nvgpu_posix_io_readl_reg_space(g,
flcn_base + falcon_falcon_dmemc_r(0));
if (nvgpu_posix_fault_injection_handle_call(
nvgpu_utf_falcon_memcpy_get_fault_injection())) {
access->value = 0;
return;
}
access->value = ctrl_r & addr_mask;
} else {
access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
}
}
struct utf_falcon *nvgpu_utf_falcon_init(struct unit_module *m,
struct gk20a *g, u32 flcn_id)
{
struct utf_falcon *utf_flcn;
struct nvgpu_falcon *flcn;
u32 flcn_size;
u32 flcn_base;
u32 hwcfg_r, hwcfg1_r, ports;
if (nvgpu_falcon_sw_init(g, flcn_id) != 0) {
unit_err(m, "nvgpu Falcon init failed!\n");
return NULL;
}
flcn = nvgpu_falcon_get_instance(g, flcn_id);
utf_flcn = (struct utf_falcon *) malloc(sizeof(struct utf_falcon));
if (!utf_flcn) {
return NULL;
}
utf_flcn->flcn = flcn;
flcn_base = flcn->flcn_base;
if (nvgpu_posix_io_add_reg_space(g,
flcn_base,
UTF_FALCON_MAX_REG_OFFSET) != 0) {
unit_err(m, "Falcon add reg space failed!\n");
goto out;
}
/*
* Initialize IMEM & DMEM size that will be needed by NvGPU for
* bounds check.
*/
hwcfg_r = flcn_base + falcon_falcon_hwcfg_r();
flcn_size = UTF_FALCON_IMEM_DMEM_SIZE / FALCON_BLOCK_SIZE;
flcn_size = (flcn_size << 9) | flcn_size;
nvgpu_posix_io_writel_reg_space(g, hwcfg_r, flcn_size);
/* set imem and dmem ports count. */
hwcfg1_r = flcn_base + falcon_falcon_hwcfg1_r();
ports = (1 << 8) | (1 << 12);
nvgpu_posix_io_writel_reg_space(g, hwcfg1_r, ports);
utf_flcn->imem = (u32 *) nvgpu_kzalloc(g, UTF_FALCON_IMEM_DMEM_SIZE);
if (utf_flcn->imem == NULL) {
unit_err(m, "Falcon imem alloc failed!\n");
goto out_reg_space;
}
utf_flcn->dmem = (u32 *) nvgpu_kzalloc(g, UTF_FALCON_IMEM_DMEM_SIZE);
if (utf_flcn->dmem == NULL) {
unit_err(m, "Falcon dmem alloc failed!\n");
goto free_imem;
}
return utf_flcn;
free_imem:
nvgpu_kfree(g, utf_flcn->imem);
out_reg_space:
nvgpu_posix_io_delete_reg_space(g, flcn_base);
out:
nvgpu_falcon_sw_free(g, flcn_id);
free(utf_flcn);
return NULL;
}
void nvgpu_utf_falcon_free(struct gk20a *g, struct utf_falcon *utf_flcn)
{
if (utf_flcn == NULL || utf_flcn->flcn == NULL)
return;
nvgpu_kfree(g, utf_flcn->dmem);
nvgpu_kfree(g, utf_flcn->imem);
nvgpu_posix_io_delete_reg_space(g, utf_flcn->flcn->flcn_base);
nvgpu_falcon_sw_free(g, utf_flcn->flcn->flcn_id);
free(utf_flcn);
}
void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, struct utf_falcon *utf_flcn,
u32 reg_data)
{
u32 flcn_base;
flcn_base = utf_flcn->flcn->flcn_base;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_dmactl_r(), reg_data);
}

55
userspace/units/falcon/falcon_utf.h Normal file
View File

@@ -0,0 +1,55 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __FALCON_UTF_H__
#define __FALCON_UTF_H__
#include <nvgpu/posix/types.h>
#include <nvgpu/posix/io.h>
#define UTF_FALCON_MAX_REG_OFFSET 0x400
#define UTF_FALCON_IMEM_DMEM_SIZE (127 * 1024)
struct gk20a;
struct nvgpu_falcon;
struct utf_falcon {
struct nvgpu_falcon *flcn;
u32 *imem;
u32 *dmem;
};
struct nvgpu_posix_fault_inj *nvgpu_utf_falcon_memcpy_get_fault_injection(void);
void nvgpu_utf_falcon_writel_access_reg_fn(struct gk20a *g,
struct utf_falcon *flcn,
struct nvgpu_reg_access *access);
void nvgpu_utf_falcon_readl_access_reg_fn(struct gk20a *g,
struct utf_falcon *flcn,
struct nvgpu_reg_access *access);
struct utf_falcon *nvgpu_utf_falcon_init(struct unit_module *m,
struct gk20a *g, u32 flcn_id);
void nvgpu_utf_falcon_free(struct gk20a *g, struct utf_falcon *utf_flcn);
void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, struct utf_falcon *utf_flcn,
u32 reg_data);
#endif

28
userspace/units/falcon/libfalcon_utf.export Normal file
View File

@@ -0,0 +1,28 @@
#
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
nvgpu_utf_falcon_free
nvgpu_utf_falcon_init
nvgpu_utf_falcon_readl_access_reg_fn
nvgpu_utf_falcon_set_dmactl
nvgpu_utf_falcon_writel_access_reg_fn
nvgpu_utf_falcon_memcpy_get_fault_injection