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git://nv-tegra.nvidia.com/linux-nvgpu.git
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Open source GPL/LGPL release
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svcmobrel-release
325
userspace/units/fb/fb_mmu_fault_gv11b_fusa.c
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325
userspace/units/fb/fb_mmu_fault_gv11b_fusa.c
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/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unit/unit.h>
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#include <unit/io.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/posix/posix-fault-injection.h>
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#include <unistd.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/nvgpu_init.h>
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#include "hal/mc/mc_gp10b.h"
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#include "hal/fb/fb_gm20b.h"
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#include "hal/fb/fb_gv11b.h"
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#include "hal/fb/fb_mmu_fault_gv11b.h"
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#include "hal/fb/intr/fb_intr_gv11b.h"
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#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
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#include "fb_fusa.h"
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#define FAULT_STATUS_TEST_VAL 0x101U
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#define TEST_VALUE_1 0x80801234
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#define TEST_VALUE_2 0xABCD4567
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static u32 hal_channel_count(struct gk20a *g)
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{
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/* Reasonable channel count for the purpose of this test */
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return 0x00000200U;
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}
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static void hal_bar2_fault_nop(struct gk20a *g)
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{
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/* no-op */
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}
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static int hal_bar2_bind_nop(struct gk20a *g, struct nvgpu_mem *bar2_inst)
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{
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/* no-op */
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return 0;
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}
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static int hal_bar2_bind_fail(struct gk20a *g, struct nvgpu_mem *bar2_inst)
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{
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return -1;
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}
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static u32 hal_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id)
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{
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return INVAL_ID;
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}
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int fb_mmu_fault_gv11b_init_test(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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/* HALs under test */
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g->ops.fb.read_mmu_fault_buffer_size =
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gv11b_fb_read_mmu_fault_buffer_size;
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g->ops.fb.read_mmu_fault_buffer_get =
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gv11b_fb_read_mmu_fault_buffer_get;
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g->ops.fb.read_mmu_fault_buffer_put =
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gv11b_fb_read_mmu_fault_buffer_put;
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g->ops.fb.write_mmu_fault_buffer_get =
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fb_gv11b_write_mmu_fault_buffer_get;
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g->ops.fb.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled;
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g->ops.fb.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw;
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g->ops.fb.write_mmu_fault_buffer_size =
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gv11b_fb_write_mmu_fault_buffer_size;
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g->ops.fb.read_mmu_fault_status = gv11b_fb_read_mmu_fault_status;
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g->ops.fb.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw;
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g->ops.fb.write_mmu_fault_buffer_lo_hi =
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gv11b_fb_write_mmu_fault_buffer_lo_hi;
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g->ops.fb.read_mmu_fault_addr_lo_hi =
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gv11b_fb_read_mmu_fault_addr_lo_hi;
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g->ops.fb.read_mmu_fault_inst_lo_hi =
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gv11b_fb_read_mmu_fault_inst_lo_hi;
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g->ops.fb.read_mmu_fault_info = gv11b_fb_read_mmu_fault_info;
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g->ops.fb.write_mmu_fault_status = gv11b_fb_write_mmu_fault_status;
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/* Other HALs that are needed */
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g->ops.channel.count = hal_channel_count;
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g->ops.ce.mthd_buffer_fault_in_bar2_fault = hal_bar2_fault_nop;
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g->ops.bus.bar2_bind = hal_bar2_bind_nop;
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g->ops.fifo.mmu_fault_id_to_pbdma_id =
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hal_fifo_mmu_fault_id_to_pbdma_id;
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g->ops.mm.mmu_fault.parse_mmu_fault_info =
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gv11b_mm_mmu_fault_parse_mmu_fault_info;
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return UNIT_SUCCESS;
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}
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int fb_mmu_fault_gv11b_buffer_test(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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u32 get_idx;
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u32 val;
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u32 lo, hi;
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struct nvgpu_posix_fault_inj *timers_fi =
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nvgpu_timers_get_fault_injection();
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if (g->ops.fb.is_fault_buf_enabled(g, 0)) {
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unit_return_fail(m, "fault buffer not disabled as expected\n");
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}
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/* Standard case */
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gv11b_fb_fault_buffer_get_ptr_update(g, 0, 0);
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/* Overflow situation */
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nvgpu_writel(g, fb_mmu_fault_buffer_get_r(0),
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fb_mmu_fault_buffer_get_overflow_m());
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gv11b_fb_fault_buffer_get_ptr_update(g, 0, 0);
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gv11b_fb_fault_buffer_size_val(g, 0);
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if (!gv11b_fb_is_fault_buffer_empty(g, 0, &get_idx)) {
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unit_return_fail(m, "fault buffer not empty as expected\n");
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}
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/* Fault buffer hw setup */
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g->ops.fb.fault_buf_configure_hw(g, 0);
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/* Enable fault buffer */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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/* Enabling again shouldn't cause an issue */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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/* Make nvgpu_timeout_init fail during disable operation */
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nvgpu_posix_enable_fault_injection(timers_fi, true, 0);
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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nvgpu_posix_enable_fault_injection(timers_fi, false, 0);
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/* Disable */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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/* Try to disable again, but cause a timeout as fault status is set */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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nvgpu_writel(g, fb_mmu_fault_status_r(),
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fb_mmu_fault_status_busy_true_f());
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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if (g->ops.fb.is_fault_buf_enabled(g, 0)) {
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unit_return_fail(m, "fault buffer not disabled as expected\n");
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}
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nvgpu_writel(g, fb_mmu_fault_addr_lo_r(), TEST_VALUE_1);
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nvgpu_writel(g, fb_mmu_fault_addr_hi_r(), TEST_VALUE_2);
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g->ops.fb.read_mmu_fault_addr_lo_hi(g, &lo, &hi);
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if ((lo != TEST_VALUE_1) || (hi != TEST_VALUE_2)) {
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unit_return_fail(m, "Invalid MMU fault address\n");
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}
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nvgpu_writel(g, fb_mmu_fault_inst_lo_r(), TEST_VALUE_1);
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nvgpu_writel(g, fb_mmu_fault_inst_hi_r(), TEST_VALUE_2);
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g->ops.fb.read_mmu_fault_inst_lo_hi(g, &lo, &hi);
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if ((lo != TEST_VALUE_1) || (hi != TEST_VALUE_2)) {
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unit_return_fail(m, "Invalid MMU fault inst\n");
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}
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val = g->ops.fb.read_mmu_fault_info(g);
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if (val != nvgpu_readl(g, fb_mmu_fault_info_r())) {
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unit_return_fail(m, "invalid fb_mmu_fault_info_r value\n");
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}
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g->ops.fb.write_mmu_fault_status(g, FAULT_STATUS_TEST_VAL);
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if (nvgpu_readl(g, fb_mmu_fault_status_r()) != FAULT_STATUS_TEST_VAL) {
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unit_return_fail(m, "invalid fb_mmu_fault_status_r value\n");
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}
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return UNIT_SUCCESS;
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}
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int fb_mmu_fault_gv11b_snap_reg(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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struct mmu_fault_info mmufault;
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/* Not a valid fault, chid should just be zero'ed out by memset */
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gv11b_mm_copy_from_fault_snap_reg(g, 0, &mmufault);
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if (mmufault.chid != 0) {
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unit_return_fail(m, "chid updated for invalid fault\n");
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}
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/* Valid fault */
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gv11b_mm_copy_from_fault_snap_reg(g, fb_mmu_fault_status_valid_set_f(),
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&mmufault);
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if (mmufault.chid != NVGPU_INVALID_CHANNEL_ID) {
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unit_return_fail(m, "chid NOT updated for valid fault\n");
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}
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return UNIT_SUCCESS;
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}
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static bool helper_is_intr_cleared(struct gk20a *g)
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{
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return (nvgpu_readl(g, fb_mmu_fault_status_r()) ==
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fb_mmu_fault_status_valid_clear_f());
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}
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int fb_mmu_fault_gv11b_handle_fault(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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u32 niso_intr;
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/* Set interrupt source as "other" and handle it */
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niso_intr = fb_niso_intr_mmu_other_fault_notify_m();
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nvgpu_writel(g, fb_mmu_fault_status_r(), 0);
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (1)\n");
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}
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/* Enable fault buffer */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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/* Handle again for branch coverage */
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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/* Set a valid dropped status and handle again */
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nvgpu_writel(g, fb_mmu_fault_status_r(),
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fb_mmu_fault_status_dropped_bar1_phys_set_f());
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (2)\n");
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}
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/* Now set interrupt source as a non-replayable fault and handle it */
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niso_intr = fb_niso_intr_mmu_nonreplayable_fault_notify_m();
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nvgpu_writel(g, fb_mmu_fault_status_r(), 0);
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (3)\n");
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}
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/* Now set source as non-replayable and overflow then handle it */
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niso_intr = fb_niso_intr_mmu_nonreplayable_fault_notify_m() |
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fb_niso_intr_mmu_nonreplayable_fault_overflow_m();
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nvgpu_writel(g, fb_mmu_fault_status_r(), 0);
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (4)\n");
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}
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/* Same case but ensure fault status register is also set properly */
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nvgpu_writel(g, fb_mmu_fault_status_r(),
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fb_mmu_fault_status_non_replayable_overflow_m());
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (5)\n");
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}
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/* Case where getptr is reported as corrupted */
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nvgpu_writel(g, fb_mmu_fault_status_r(),
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fb_mmu_fault_status_non_replayable_overflow_m() |
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fb_mmu_fault_status_non_replayable_getptr_corrupted_m());
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gv11b_fb_handle_mmu_fault(g, niso_intr);
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if (!helper_is_intr_cleared(g)) {
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unit_return_fail(m, "unhandled interrupt (6)\n");
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}
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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return UNIT_SUCCESS;
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}
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int fb_mmu_fault_gv11b_handle_bar2_fault(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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struct mmu_fault_info mmufault;
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struct nvgpu_channel refch;
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u32 fault_status = 0;
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static const char *const error_str = "test error";
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(void) memset(&mmufault, 0, sizeof(mmufault));
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(void) memset(&refch, 0, sizeof(refch));
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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/* Set the minimum mmufault struct to handle the fault */
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/* First cover some error cases */
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gv11b_fb_mmu_fault_info_dump(g, NULL);
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gv11b_fb_mmu_fault_info_dump(g, &mmufault);
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/* Now set it up properly */
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mmufault.valid = true;
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mmufault.refch = &refch;
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mmufault.fault_type_desc = error_str;
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mmufault.client_type_desc = error_str;
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mmufault.client_id_desc = error_str;
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gv11b_fb_mmu_fault_info_dump(g, &mmufault);
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fault_status = fb_mmu_fault_status_non_replayable_error_m();
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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/* Case where g->ops.bus.bar2_bind fails */
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g->ops.bus.bar2_bind = hal_bar2_bind_fail;
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_ENABLED);
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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g->ops.bus.bar2_bind = hal_bar2_bind_nop;
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/* Case where fault buffer is not enabled */
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g->ops.fb.fault_buf_set_state_hw(g, 0, NVGPU_MMU_FAULT_BUF_DISABLED);
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gv11b_fb_handle_bar2_fault(g, &mmufault, fault_status);
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return UNIT_SUCCESS;
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}
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