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Open source GPL/LGPL release
This commit is contained in:
svcmobrel-release
422
userspace/units/fifo/engine/nvgpu-engine.h
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422
userspace/units/fifo/engine/nvgpu-engine.h
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/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef UNIT_NVGPU_ENGINE_H
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#define UNIT_NVGPU_ENGINE_H
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#include <nvgpu/types.h>
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struct unit_module;
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struct gk20a;
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/** @addtogroup SWUTS-fifo-engine
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* @{
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*
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* Software Unit Test Specification for fifo/engine
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*/
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/**
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* Test specification for: test_engine_setup_sw
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*
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* Description: Branch coverage for nvgpu_engine_setup/cleanup_sw.
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_engine_setup_sw, nvgpu_engine_cleanup_sw
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*
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* Input: None
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*
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* Steps:
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* - Check valid case for nvgpu_engine_setup_sw.
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* - Check valid case for nvgpu_engine_cleanup_sw.
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* - Check invalid case for nvgpu_engine_setup_sw.
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* - Failure to allocate engine contexts (w/ fault injection)
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* - Failure to allocate active engines list (w/ fault injection)
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* - Failure to initialize engine info (using stub for
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* g->ops.engine.init_info)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_setup_sw(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_init_info
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*
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* Description: Branch coverage for nvgpu_engine_init_info
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_engine_init_info
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - Check valid cases for nvgpu_engine_init_info using gv11b HALs.
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* - Check that function returns 0 and that number of engines is > 0.
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* - Check invalid cases for nvgpu_engine_init_info:
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* - g->ops.top.get_device_info is NULL
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* - g->ops.top.get_device_info returns failure
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* - g->ops.pbdma.find_for_runlist fails to find PBDMA servicing the engine.
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* - Check that function returns < 0 and that number of engines is 0.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_init_info(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_ids
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*
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* Description: Branch coverage for engine ids
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_engine_get_ids, nvgpu_engine_check_valid_id,
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* nvgpu_engine_get_gr_id
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - Check nvgpu_engine_check_valid_id returns false for U32_MAX
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* - Get engine ids for all engine enums in NVGPU_ENGINE_GR to
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* NVGPU_ENGINE_INVAL
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* - Check that all returned ids are valid with nvgpu_engine_check_valid_id.
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* - Check that nvgpu_engine_get_gr_id is in the returned ids for
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* NVGPU_ENGINE_GR
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* - Build a mask of CE engines (for other test use)
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* - Build a mask of active engines (for other test use)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_ids(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_get_fast_ce_runlist_id
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*
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* Description: Get Asynchronous CE runlist id
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_get_fast_ce_runlist_id
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - Check that nvgpu_engine_get_fast_ce_runlist_id returns valid id.
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* - Check that NVGPU_INVALID_ENG_ID is returned when g is NULL.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_get_fast_ce_runlist_id(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_nvgpu_engine_get_gr_runlist_id
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*
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* Description: Get GR runlist id
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_get_gr_runlist_id
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - Check that nvgpu_engine_get_gr_runlist_id returns valid id.
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* - Check case where NVGPU_ENGINE_GR is not found.
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* - Check case where an entry is found for NVGPU_ENGINE_GR, but
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* the HW engine_id is invalid.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_get_gr_runlist_id(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_is_valid_runlist_id
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*
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* Description: Check is runlist Id is valid
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_is_valid_runlist_id
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - Check that nvgpu_engine_is_valid_runlist_id returns true for
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* active engines's runlist_id.
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* - Check that false is returned when g is NULL.
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* - Check that false is returned for NVGPU_INVALID_RUNLIST_ID.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_is_valid_runlist_id(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_get_active_eng_info
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*
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* Description: Branch coverage for nvgpu_engine_get_active_eng_info
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_engine_get_active_eng_info, nvgpu_engine_check_valid_id
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*
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* Input: test_engine_ids must have run.
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*
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* Steps:
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* - For each H/W engine id, call nvgpu_engine_get_active_eng_info:
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* - Check that info is non NULL for active engines.
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* - Check that info is NULL for inactive engines.
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* - Check that nvgpu_engine_get_active_eng_info returns NULL when g == NULL.
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* - Check that nvgpu_engine_get_active_eng_info returns NULL when f->max_engines == 0.
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* - Check that nvgpu_engine_get_active_eng_info returns NULL when f->num_engines == 0.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_get_active_eng_info(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_enum_from_type
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*
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* Description: Branch coverage for nvgpu_engine_enum_from_type
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_engine_enum_from_type
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*
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* Input: test_engine_ids must have run.
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*
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* Steps:
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* - For each HW enum type, call nvgpu_engine_enum_from_type.
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* - Check that NVGPU_ENGINE_GR is returned for
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* top_device_info_type_enum_graphics_v().
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* - Check that NVGPU_ENGINE_ASYNC_CE is returned for
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* top_device_info_type_enum_lce_v().
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* - Check that NVGPU_ENGINE_INVAL is returned for other values.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_enum_from_type(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_interrupt_mask
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*
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* Description: Engine interrupt masks
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*
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* Test Type: Feature
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*
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* Targets: nvgpu_gr_engine_interrupt_mask, nvgpu_ce_engine_interrupt_mask,
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* nvgpu_engine_act_interrupt_mask, nvgpu_engine_get_all_ce_reset_mask
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*
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* Input: test_engine_ids must have run.
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*
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* Steps:
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* - Get interrupt mask for all engines using ngpu_engine_interrupt_mask.
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* - Check that engine_intr_mask in non NULL
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* - For each active engine, get interrupt mask with
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* nvgpu_engine_act_interrupt_mask.
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* - Check that mask in non NULL
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* - Check that mask is contained in engine_intr_mask.
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* - Check that engine_intr_mask only contains active engines
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* - Get CE reset mask using nvgpu_engine_get_all_ce_reset_mask
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* - Check that ce_reset_mask == ce_mask (from unit context)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_interrupt_mask(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_mmu_fault_id
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*
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* Description: Engine ID to MMU fault ID conversions
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_id_to_mmu_fault_id,
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* nvgpu_engine_mmu_fault_id_to_engine_id
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - For each engine_id (including invalid one)
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* - Get engine_info using nvgpu_engine_get_active_eng_info.
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* - Get fault_id using nvgpu_engine_id_to_mmu_fault_id.
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* - For valid engine ids, check that fault_id matches the one
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* from engine_info, else check that returned fault_id is invalid.
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* - Get engine_id using nvgpu_engine_mmu_fault_id_to_engine_id.
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* - For valid engine ids, check that engine_id matches the one
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* from engine_info, else check that returned engine_id is invalid.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_mmu_fault_id(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_mmu_fault_id_veid
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*
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* Description: Engine ID to MMU fault ID conversions
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_mmu_fault_id_to_veid,
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* nvgpu_engine_mmu_fault_id_to_eng_id_and_veid,
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* nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id,
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* nvgpu_engine_runqueue_sel
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - For each engine_id (including invalid one)
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* - Get engine_info using nvgpu_engine_get_active_eng_info.
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* - Get fault_id using nvgpu_engine_id_to_mmu_fault_id.
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* - Get engine_id using nvgpu_engine_mmu_fault_id_to_engine_id and
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* nvgpu_engine_mmu_fault_id_to_eng_id_and_veid.
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* - For valid engine ids, check that engine_id matches the one
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* from engine_info, else check that returned engine_id is invalid.
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*
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* - Cover the following cases for nvgpu_engine_mmu_fault_id_to_veid:
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* - gr_eng_fault_id <= mmu_fault_id < (gr_eng_fault_id + num_subctx),
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* returned veid should be in [0..num_subctx-1] range.
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* - mmu_fault_id out of above range, in which case returned veid
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* must be INVAL_ID.
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*
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* - Call nvgpu_engine_mmu_fault_id_to_eng_id_and_veid for all
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* possible GR MMU fault ids, and check that function returns
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* GR's active engine id, and sets veid properly.
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* MMU fault id, and check that function returns CE's active
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* engine id, but veid is not set.
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* - Call nvgpu_engine_mmu_fault_id_to_eng_id_and_veid for a CE
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* MMU fault id, and check that function returns CE's active
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* engine id, but veid is not set.
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*
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* - Check that nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id looks
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* up pbdma_id when active engine id was found. Check that it
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* returns invalid PBDMA id otherwise.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_mmu_fault_id_veid(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_get_mask_on_id
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*
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* Description: Get mask of engines TSG/ch is loaded on
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_get_mask_on_id, nvgpu_engine_get_id_and_type
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*
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* Input: test_engine_ids must have run.
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*
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* Steps:
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* - Call nvgpu_engine_get_mask_on_id with a combination of type
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* (TSG or channel), and incrementing the id.
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* - Using a stub for g->ops.engine_status.read_engine_status_info,
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* cover the following cases:
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* - Engine is busy or idle.
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* - Context switch is loading a context, or not (which determines
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* whether to check against ctx_next_id or ctx_id).
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* - Context on engine has the same type (TSG/ch) or not.
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* - Context on engine has the same id, or not.
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* - Check that nvgpu_engine_get_id_and_type returns expected id and type.
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* - Check that the mask is only set when engine is busy, and
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* context has same id and type.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_get_mask_on_id(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_find_busy_doing_ctxsw
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*
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* Description: Find busy engine doing context switch
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*
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* Test Type: Feature based
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*
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* Targets: nvgpu_engine_find_busy_doing_ctxsw
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
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* - Use stub for g->ops.engine_status.read_engine_status_info, to
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* emulate engine status:
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* - Busy/idle state.
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* - Context switch status (VALID, LOAD or SAVE).
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* - Set ctx_id and ctx_id_type as per context switch status.
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* - Set ctx_next_id and ctx_next_id_type as per context switch status.
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* - Use stub for g->ops.gr.falcon_read_fecs_ctxsw_mailbox, to
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* emulate current FECS method.
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* - Call nvgpu_engine_find_busy_doing_ctxsw, and check that:
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* - When engine is idle, or not doing a context switch,
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* NVGPU_INVALID_ENG_ID is returned, and other parameters
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* are not modified.
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* - When engine is busy and doing a context switch, engine_id
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* is returned, is_tsg is true and id matches expected TSG id.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_find_busy_doing_ctxsw(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
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* Test specification for: test_engine_get_runlist_busy_engines
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||||
*
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||||
* Description: Get busy engines serviced by a given runlist
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*
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* Test Type: Feature based
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||||
*
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* Targets: nvgpu_engine_get_runlist_busy_engines
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*
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* Input: test_fifo_init_support must have run.
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*
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* Steps:
|
||||
* - Use stub for g->ops.engine_status.read_engine_status_info, to
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* emulate busy/idle state for engine.
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* - Build f->engine_info and f->active_engines_list, to cover the
|
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* following cases for nvgpu_engine_get_runlist_busy_engines:
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* - Engine has same runlist_id, and is busy.
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* - Engine has same runlist_id, but is idle.
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* - No engine with matching runlist_id was found.
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* - No engine at all (f->num_engines = 0).
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* - Check that returned mask is non-zero only for the first case
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* (busy and matching runlist_id).
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_engine_get_runlist_busy_engines(struct unit_module *m,
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struct gk20a *g, void *args);
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/**
|
||||
* @}
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||||
*/
|
||||
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||||
#endif /* UNIT_NVGPU_ENGINE_H */
|
||||
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