Open source GPL/LGPL release

userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = flush-gk20a-fusa.o
+MODULE = flush-gk20a-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=flush-gk20a-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/cache/flush_gk20a_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=flush-gk20a-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c

@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/vm.h>
+#include <nvgpu/nvgpu_init.h>
+
+#include "os/posix/os_posix.h"
+
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+
+#include "hal/mm/cache/flush_gk20a.h"
+
+#include <nvgpu/hw/gv11b/hw_flush_gv11b.h>
+
+#include <nvgpu/posix/posix-fault-injection.h>
+#include <nvgpu/posix/dma.h>
+
+#include "flush-gk20a-fusa.h"
+
+/*
+ * Write callback (for all nvgpu_writel calls).
+ */
+#define WR_FLUSH_0	0
+#define WR_FLUSH_1	1
+#define WR_FLUSH_2	2
+#define WR_FLUSH_3	3
+#define WR_FLUSH_ACTUAL				0
+#define WR_FLUSH_TEST_FB_FLUSH_ADDR		1
+#define WR_FLUSH_TEST_L2_FLUSH_DIRTY_ADDR	2
+#define WR_FLUSH_TEST_L2_SYSTEM_INVALIDATE	3
+
+static u32 write_specific_value;
+static u32 write_specific_addr;
+
+static void writel_access_reg_fn(struct gk20a *g,
+			     struct nvgpu_reg_access *access)
+{
+	if (((write_specific_addr == WR_FLUSH_TEST_FB_FLUSH_ADDR) &&
+			(access->addr == flush_fb_flush_r())) ||
+		((write_specific_addr == WR_FLUSH_TEST_L2_FLUSH_DIRTY_ADDR) &&
+			(access->addr == flush_l2_flush_dirty_r())) ||
+		((write_specific_addr == WR_FLUSH_TEST_L2_SYSTEM_INVALIDATE) &&
+			(access->addr == flush_l2_system_invalidate_r()))) {
+		nvgpu_posix_io_writel_reg_space(g, access->addr,
+							write_specific_value);
+	} else {
+		nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+	}
+}
+
+/*
+ * Read callback, similar to the write callback above.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+			    struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+/*
+ * Define all the callbacks to be used during the test. Typically all
+ * write operations use the same callback, likewise for all read operations.
+ */
+static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+};
+
+static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
+{
+	if (is_iGPU) {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	} else {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
+	}
+}
+
+static int init_mm(struct unit_module *m, struct gk20a *g)
+{
+	u64 low_hole, aperture_size;
+	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
+	struct mm_gk20a *mm = &g->mm;
+
+	p->mm_is_iommuable = true;
+
+	/* Minimum HALs for page_table */
+	g->ops.mm.gmmu.get_default_big_page_size =
+					nvgpu_gmmu_default_big_page_size;
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
+	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
+	g->ops.ramin.init_pdb = gv11b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
+	g->ops.mm.mmu_fault.info_mem_destroy =
+					gv11b_mm_mmu_fault_info_mem_destroy;
+
+	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
+
+	/* Register space: FB_MMU */
+	if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x800) != 0) {
+		unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
+	}
+
+	/*
+	 * Initialize VM space for system memory to be used throughout this
+	 * unit module.
+	 * Values below are similar to those used in nvgpu_init_system_vm()
+	 */
+	low_hole = SZ_4K * 16UL;
+	aperture_size = GK20A_PMU_VA_SIZE;
+	mm->pmu.aperture_size = GK20A_PMU_VA_SIZE;
+
+	mm->pmu.vm = nvgpu_vm_init(g,
+				   g->ops.mm.gmmu.get_default_big_page_size(),
+				   low_hole,
+				   0ULL,
+				   nvgpu_safe_sub_u64(aperture_size, low_hole),
+				   0ULL,
+				   true,
+				   false,
+				   false,
+				   "system");
+	if (mm->pmu.vm == NULL) {
+		unit_return_fail(m, "'system' nvgpu_vm_init failed\n");
+	}
+
+	/*
+	 * This initialization will make sure that correct aperture mask
+	 * is returned */
+	g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM;
+	g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
+
+	return UNIT_SUCCESS;
+}
+
+int test_env_init_flush_gk20a_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+
+	init_platform(m, g, true);
+
+	if (init_mm(m, g) != 0) {
+		unit_return_fail(m, "nvgpu_init_mm_support failed\n");
+	}
+
+	write_specific_value = 0;
+	write_specific_addr = 0;
+
+	return UNIT_SUCCESS;
+}
+
+#define F_GK20A_FB_FLUSH_DEFAULT_INPUT			0
+#define F_GK20A_FB_FLUSH_GET_RETRIES			1
+#define F_GK20A_FB_FLUSH_PENDING_TRUE			2
+#define F_GK20A_FB_FLUSH_OUTSTANDING_TRUE		3
+#define F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE	4
+#define F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO		5
+#define F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF		6
+
+const char *m_gk20a_mm_fb_flush_str[] = {
+	"default_input",
+	"get_flush_retries",
+	"fb_flush_pending_true",
+	"fb_flush_outstanding_true",
+	"fb_flush_outstanding_pending_true",
+	"nvgpu_powered_off",
+};
+
+static u32 stub_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op)
+{
+	return 100U;
+}
+
+static void stub_fb_dump_vpr_info(struct gk20a *g)
+{
+}
+
+static void stub_fb_dump_wpr_info(struct gk20a *g)
+{
+}
+
+int test_gk20a_mm_fb_flush(struct unit_module *m, struct gk20a *g, void *args)
+{
+	int err;
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON);
+	write_specific_addr = WR_FLUSH_TEST_FB_FLUSH_ADDR;
+
+	switch (branch) {
+	case F_GK20A_FB_FLUSH_PENDING_TRUE:
+		write_specific_value = WR_FLUSH_1;
+		break;
+	case F_GK20A_FB_FLUSH_OUTSTANDING_TRUE:
+		write_specific_value = WR_FLUSH_2;
+		break;
+	case F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE:
+		write_specific_value = WR_FLUSH_3;
+		break;
+	case F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO:
+		write_specific_value = WR_FLUSH_1;
+		break;
+	default:
+		write_specific_value = WR_FLUSH_0;
+		break;
+	}
+
+	g->ops.mm.get_flush_retries = branch == F_GK20A_FB_FLUSH_GET_RETRIES ?
+			stub_mm_get_flush_retries : NULL;
+
+	g->ops.fb.dump_vpr_info = branch == F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO ?
+			stub_fb_dump_vpr_info : NULL;
+
+	g->ops.fb.dump_wpr_info = branch == F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO ?
+			stub_fb_dump_wpr_info : NULL;
+
+	if (branch == F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF) {
+		nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF);
+	}
+
+	err = gk20a_mm_fb_flush(g);
+
+	if ((branch == F_GK20A_FB_FLUSH_PENDING_TRUE) ||
+		(branch == F_GK20A_FB_FLUSH_OUTSTANDING_TRUE) ||
+		(branch == F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE) ||
+		(branch == F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO)) {
+		unit_assert(err != 0, goto done);
+	} else {
+		unit_assert(err == 0, goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed at %s\n", __func__,
+					m_gk20a_mm_fb_flush_str[branch]);
+	}
+	write_specific_addr = WR_FLUSH_ACTUAL;
+	return ret;
+}
+
+#define F_GK20A_L2_FLUSH_DEFAULT_INPUT			0
+#define F_GK20A_L2_FLUSH_GET_RETRIES			1
+#define F_GK20A_L2_FLUSH_PENDING_TRUE			2
+#define F_GK20A_L2_FLUSH_OUTSTANDING_TRUE		3
+#define F_GK20A_L2_FLUSH_INVALIDATE			4
+#define F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF		5
+
+const char *m_gk20a_mm_l2_flush_str[] = {
+	"default_input",
+	"get_flush_retries",
+	"l2_flush_pending_true",
+	"l2_flush_outstanding_true",
+	"l2_flush_invalidate",
+	"nvgpu_powered_off",
+};
+
+int test_gk20a_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args)
+{
+	int err;
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+	bool invalidate;
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON);
+	write_specific_addr = WR_FLUSH_TEST_L2_FLUSH_DIRTY_ADDR;
+
+	switch (branch) {
+	case F_GK20A_L2_FLUSH_PENDING_TRUE:
+		write_specific_value = WR_FLUSH_1;
+		break;
+	case F_GK20A_L2_FLUSH_OUTSTANDING_TRUE:
+		write_specific_value = WR_FLUSH_2;
+		break;
+	default:
+		write_specific_value = WR_FLUSH_0;
+		break;
+	}
+
+	g->ops.mm.get_flush_retries = (branch == F_GK20A_L2_FLUSH_GET_RETRIES) ?
+			stub_mm_get_flush_retries : NULL;
+
+	invalidate = (branch == F_GK20A_L2_FLUSH_INVALIDATE) ? true : false;
+
+	if (branch == F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF) {
+		nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF);
+	}
+
+	err = gk20a_mm_l2_flush(g, invalidate);
+
+	if ((branch == F_GK20A_L2_FLUSH_PENDING_TRUE) ||
+		(branch == F_GK20A_L2_FLUSH_OUTSTANDING_TRUE)) {
+		unit_assert(err != 0, goto done);
+	} else {
+		unit_assert(err == 0, goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed at %s\n", __func__,
+					m_gk20a_mm_l2_flush_str[branch]);
+	}
+	write_specific_addr = WR_FLUSH_ACTUAL;
+	return ret;
+}
+
+#define F_GK20A_L2_INVALIDATE_DEFAULT_INPUT	0
+#define F_GK20A_L2_INVALIDATE_PENDING_TRUE	1
+#define F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE	2
+#define F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL	3
+#define F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF	4
+
+
+const char *m_gk20a_mm_l2_invalidate_str[] = {
+	"invalidate_default_input",
+	"invalidate_l2_pending_true",
+	"invalidate_l2_outstanding_true",
+	"invalidate_get_flush_retries_null",
+};
+
+static u32 global_count = 100;
+static u32 count;
+
+static u32 stub_mm_get_flush_retries_count(struct gk20a *g,
+							enum nvgpu_flush_op op)
+{
+	count = global_count++;
+	return 100U;
+}
+
+int test_gk20a_mm_l2_invalidate(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON);
+	write_specific_addr = WR_FLUSH_TEST_L2_SYSTEM_INVALIDATE;
+
+	switch (branch) {
+	case F_GK20A_L2_INVALIDATE_PENDING_TRUE:
+		write_specific_value = WR_FLUSH_1;
+		break;
+	case F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE:
+		write_specific_value = WR_FLUSH_2;
+		break;
+	default:
+		write_specific_value = WR_FLUSH_0;
+		break;
+	}
+
+	g->ops.mm.get_flush_retries =
+			(branch == F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL) ?
+			NULL : stub_mm_get_flush_retries_count;
+
+	if (branch == F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF) {
+		nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF);
+	}
+
+	gk20a_mm_l2_invalidate(g);
+
+	if (branch != F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL) {
+		unit_assert(count == (global_count - 1U), goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed at %s\n", __func__,
+					m_gk20a_mm_l2_invalidate_str[branch]);
+	}
+	write_specific_addr = WR_FLUSH_ACTUAL;
+	return ret;
+}
+
+int test_env_clean_flush_gk20a_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+
+	nvgpu_vm_put(g->mm.pmu.vm);
+
+	return UNIT_SUCCESS;
+}
+
+struct unit_module_test mm_flush_gk20a_fusa_tests[] = {
+	UNIT_TEST(env_init, test_env_init_flush_gk20a_fusa, NULL, 0),
+	UNIT_TEST(mm_fb_flush_s0, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_DEFAULT_INPUT, 0),
+	UNIT_TEST(mm_fb_flush_s1, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_GET_RETRIES, 0),
+	UNIT_TEST(mm_fb_flush_s2, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_PENDING_TRUE, 0),
+	UNIT_TEST(mm_fb_flush_s3, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_OUTSTANDING_TRUE, 0),
+	UNIT_TEST(mm_fb_flush_s4, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE, 0),
+	UNIT_TEST(mm_fb_flush_s5, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO, 0),
+	UNIT_TEST(mm_fb_flush_s6, test_gk20a_mm_fb_flush, (void *)F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF, 0),
+	UNIT_TEST(mm_l2_flush_s0, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_DEFAULT_INPUT, 0),
+	UNIT_TEST(mm_l2_flush_s1, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_GET_RETRIES, 0),
+	UNIT_TEST(mm_l2_flush_s2, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_PENDING_TRUE, 0),
+	UNIT_TEST(mm_l2_flush_s3, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_OUTSTANDING_TRUE, 0),
+	UNIT_TEST(mm_l2_flush_s4, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_INVALIDATE, 0),
+	UNIT_TEST(mm_l2_flush_s5, test_gk20a_mm_l2_flush, (void *)F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF, 0),
+	UNIT_TEST(mm_l2_invalidate_s0, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_DEFAULT_INPUT, 0),
+	UNIT_TEST(mm_l2_invalidate_s1, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_PENDING_TRUE, 0),
+	UNIT_TEST(mm_l2_invalidate_s2, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE, 0),
+	UNIT_TEST(mm_l2_invalidate_s3, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL, 0),
+	UNIT_TEST(mm_l2_invalidate_s4, test_gk20a_mm_l2_invalidate, (void *)F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF, 0),
+	UNIT_TEST(env_clean, test_env_clean_flush_gk20a_fusa, NULL, 0),
+};
+
+UNIT_MODULE(flush_gk20a_fusa, mm_flush_gk20a_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.h

@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_CACHE_FLUSH_GK20A_FUSA_H
+#define UNIT_MM_HAL_CACHE_FLUSH_GK20A_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-cache-flush-gk20a-fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.cache.flush_gk20a_fusa
+ */
+
+/**
+ * Test specification for: test_env_init_flush_gk20a_fusa
+ *
+ * Description: Initialize environment for MM tests
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Init HALs and initialize VMs similar to nvgpu_init_system_vm().
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_init_flush_gk20a_fusa(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_gk20a_mm_fb_flush
+ *
+ * Description: Test FB flush
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm_cache.fb_flush, gk20a_mm_fb_flush,
+ * gops_mm.get_flush_retries
+ *
+ * Input: test_env_init, args (value can be F_GK20A_FB_FLUSH_DEFAULT_INPUT,
+ *        F_GK20A_FB_FLUSH_GET_RETRIES, F_GK20A_FB_FLUSH_PENDING_TRUE,
+ *        F_GK20A_FB_FLUSH_OUTSTANDING_TRUE,
+ *        F_GK20A_FB_FLUSH_OUTSTANDING_PENDING_TRUE,
+ *        F_GK20A_FB_FLUSH_DUMP_VPR_WPR_INFO or
+ *        F_GK20A_FB_FLUSH_NVGPU_POWERED_OFF)
+ *
+ * Steps:
+ * - Invoke FB flush command
+ * - Test FB flush with various scenarios as below:
+ *   - flush outstanding, flush pending, GPU powered off
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gk20a_mm_fb_flush(struct unit_module *m, struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gk20a_mm_l2_flush
+ *
+ * Description: Test L2 flush
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm_cache.l2_flush, gk20a_mm_l2_flush,
+ * gk20a_mm_l2_invalidate_locked
+ *
+ * Input: test_env_init, args (value can be F_GK20A_L2_FLUSH_DEFAULT_INPUT,
+ *        F_GK20A_L2_FLUSH_GET_RETRIES, F_GK20A_L2_FLUSH_PENDING_TRUE,
+ *        F_GK20A_L2_FLUSH_OUTSTANDING_TRUE, F_GK20A_L2_FLUSH_INVALIDATE or
+ *        F_GK20A_L2_FLUSH_NVGPU_POWERED_OFF)
+ *
+ * Steps:
+ * - Invoke L2 flush command
+ * - Test L2 flush with various scenarios as below:
+ *   - flush dirty outstanding, flush dirty pending, GPU powered off,
+ *     flush with invalidate
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gk20a_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gk20a_mm_l2_invalidate
+ *
+ * Description: Test L2 invalidate
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm_cache.l2_invalidate, gk20a_mm_l2_invalidate,
+ * gk20a_mm_l2_invalidate_locked
+ *
+ * Input: test_env_init, args (value can be F_GK20A_L2_INVALIDATE_DEFAULT_INPUT,
+ *        F_GK20A_L2_INVALIDATE_PENDING_TRUE,
+ *        F_GK20A_L2_INVALIDATE_OUTSTANDING_TRUE,
+ *        F_GK20A_L2_INVALIDATE_GET_RETRIES_NULL or
+ *        F_GK20A_L2_INVALIDATE_NVGPU_POWERED_OFF)
+ *
+ * Steps:
+ * - Invoke L2 invalidate
+ * - Test when invalidate is outstanding and/or pending
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gk20a_mm_l2_invalidate(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_env_clean_flush_gk20a_fusa
+ *
+ * Description: Cleanup test environment
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Destroy memory and VMs initialized for the test.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_clean_flush_gk20a_fusa(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_CACHE_FLUSH_GK20A_FUSA_H */

userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = flush-gv11b-fusa.o
+MODULE = flush-gv11b-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=flush-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/cache/flush_gv11b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=flush-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/vm.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/nvgpu_init.h>
+
+#include "os/posix/os_posix.h"
+
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+
+#include "hal/mm/cache/flush_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_flush_gv11b.h>
+
+#include <nvgpu/posix/posix-fault-injection.h>
+#include <nvgpu/posix/dma.h>
+
+#include "flush-gv11b-fusa.h"
+
+/*
+ * Write callback (for all nvgpu_writel calls).
+ */
+#define WR_FLUSH_0	0
+#define WR_FLUSH_1	1
+
+static u32 write_specific_value;
+
+static void writel_access_reg_fn(struct gk20a *g,
+			     struct nvgpu_reg_access *access)
+{
+	if (access->addr == flush_l2_flush_dirty_r()) {
+		nvgpu_posix_io_writel_reg_space(g, access->addr,
+							write_specific_value);
+	} else {
+		nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+	}
+}
+
+/*
+ * Read callback, similar to the write callback above.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+			    struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+/*
+ * Define all the callbacks to be used during the test. Typically all
+ * write operations use the same callback, likewise for all read operations.
+ */
+static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+};
+
+static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
+{
+	if (is_iGPU) {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	} else {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
+	}
+}
+
+static int init_mm(struct unit_module *m, struct gk20a *g)
+{
+	u64 low_hole, aperture_size;
+	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
+	struct mm_gk20a *mm = &g->mm;
+
+	p->mm_is_iommuable = true;
+
+	/* Minimum HALs for page_table */
+	g->ops.mm.gmmu.get_default_big_page_size =
+					nvgpu_gmmu_default_big_page_size;
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
+	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
+	g->ops.ramin.init_pdb = gv11b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
+	g->ops.mm.mmu_fault.info_mem_destroy =
+					gv11b_mm_mmu_fault_info_mem_destroy;
+
+	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
+
+	/* Register space: FB_MMU */
+	if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x800) != 0) {
+		unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
+	}
+
+	/*
+	 * Initialize VM space for system memory to be used throughout this
+	 * unit module.
+	 * Values below are similar to those used in nvgpu_init_system_vm()
+	 */
+	low_hole = SZ_4K * 16UL;
+	aperture_size = GK20A_PMU_VA_SIZE;
+	mm->pmu.aperture_size = GK20A_PMU_VA_SIZE;
+
+	mm->pmu.vm = nvgpu_vm_init(g,
+				   g->ops.mm.gmmu.get_default_big_page_size(),
+				   low_hole,
+				   0ULL,
+				   nvgpu_safe_sub_u64(aperture_size, low_hole),
+				   0ULL,
+				   true,
+				   false,
+				   false,
+				   "system");
+	if (mm->pmu.vm == NULL) {
+		unit_return_fail(m, "'system' nvgpu_vm_init failed\n");
+	}
+
+	/* BAR1 memory space */
+	mm->bar1.aperture_size = U32(16) << 20U;
+	mm->bar1.vm = nvgpu_vm_init(g,
+		g->ops.mm.gmmu.get_default_big_page_size(),
+		SZ_4K, 0ULL, nvgpu_safe_sub_u64(mm->bar1.aperture_size, SZ_4K),
+		0ULL, false, false, false, "bar1");
+	if (mm->bar1.vm == NULL) {
+		unit_return_fail(m, "'bar1' nvgpu_vm_init failed\n");
+	}
+
+	/*
+	 * This initialization will make sure that correct aperture mask
+	 * is returned */
+	g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM;
+	g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
+
+	return UNIT_SUCCESS;
+}
+
+int test_env_init_flush_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+
+	init_platform(m, g, true);
+
+	if (init_mm(m, g) != 0) {
+		unit_return_fail(m, "nvgpu_init_mm_support failed\n");
+	}
+
+	write_specific_value = 0;
+
+	return UNIT_SUCCESS;
+}
+
+#define F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL	0
+#define F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL		1
+#define F_GV11B_L2_FLUSH_FB_FLUSH_FAIL			2
+#define F_GV11B_L2_FLUSH_L2_FLUSH_FAIL			3
+#define F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL		4
+#define F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL			5
+
+const char *m_gv11b_mm_l2_flush_str[] = {
+	"pass_bar1_bind_not_null",
+	"pass_bar1_bind_null",
+	"fb_flush_fail",
+	"l2_flush_fail",
+	"tlb_invalidate_fail",
+	"fb_flush_2_fail",
+};
+
+static u32 stub_fb_flush_fail;
+static bool stub_tlb_invalidate_fail;
+
+static int stub_mm_fb_flush(struct gk20a *g)
+{
+	if (stub_fb_flush_fail == 0) {
+		return -EBUSY;
+	}
+
+	stub_fb_flush_fail--;
+	return 0;
+}
+
+static int stub_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
+{
+	return 0;
+}
+
+static int stub_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
+{
+	if (stub_tlb_invalidate_fail) {
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+int test_gv11b_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args)
+{
+	struct gpu_ops gops = g->ops;
+	int err;
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON);
+	g->ops.mm.cache.fb_flush = stub_mm_fb_flush;
+	g->ops.fb.tlb_invalidate = stub_fb_tlb_invalidate;
+
+	stub_fb_flush_fail = (branch == F_GV11B_L2_FLUSH_FB_FLUSH_FAIL) ?
+		0U : (branch == F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL ? 1U : 2U);
+
+	/* Write data to flush dirty addr will control l2_flush() output */
+	write_specific_value = branch == F_GV11B_L2_FLUSH_L2_FLUSH_FAIL ?
+			WR_FLUSH_1 : WR_FLUSH_0;
+
+	g->ops.bus.bar1_bind =
+		((branch == F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL) ||
+				(branch == F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL)) ?
+		NULL : stub_bus_bar1_bind;
+
+	stub_tlb_invalidate_fail =
+		branch == F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL ? true : false;
+
+	err = gv11b_mm_l2_flush(g, false);
+
+	unit_info(m, "%p\n", g->mm.bar1.vm->pdb.mem);
+
+	if ((branch == F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL) ||
+			(branch == F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL)) {
+		unit_assert(err == 0, goto done);
+	} else {
+		unit_assert(err != 0, goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed at %s\n", __func__,
+					m_gv11b_mm_l2_flush_str[branch]);
+	}
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF);
+	g->ops = gops;
+	return ret;
+}
+
+int test_env_clean_flush_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+
+	nvgpu_vm_put(g->mm.pmu.vm);
+	nvgpu_vm_put(g->mm.bar1.vm);
+
+	return UNIT_SUCCESS;
+}
+
+struct unit_module_test mm_flush_gv11b_fusa_tests[] = {
+	UNIT_TEST(env_init, test_env_init_flush_gv11b_fusa, NULL, 0),
+	UNIT_TEST(mm_l2_flush_s0, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL, 0),
+	UNIT_TEST(mm_l2_flush_s1, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL, 0),
+	UNIT_TEST(mm_l2_flush_s2, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_FB_FLUSH_FAIL, 0),
+	UNIT_TEST(mm_l2_flush_s3, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_L2_FLUSH_FAIL, 0),
+	UNIT_TEST(mm_l2_flush_s4, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL, 0),
+	UNIT_TEST(mm_l2_flush_s5, test_gv11b_mm_l2_flush, (void *)F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL, 0),
+	UNIT_TEST(env_clean, test_env_clean_flush_gv11b_fusa, NULL, 0),
+};
+
+UNIT_MODULE(flush_gv11b_fusa, mm_flush_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.h

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_CACHE_FLUSH_GV11B_FUSA_H
+#define UNIT_MM_HAL_CACHE_FLUSH_GV11B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-cache-flush-gv11b-fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.cache.flush_gv11b_fusa
+ */
+
+/**
+ * Test specification for: test_env_init_flush_gv11b_fusa
+ *
+ * Description: Initialize environment for MM tests
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Init HALs and initialize VMs similar to nvgpu_init_system_vm().
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_init_flush_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+	void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_l2_flush
+ *
+ * Description: Test L2 flush
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm_cache.l2_flush, gv11b_mm_l2_flush
+ *
+ * Input: test_env_init, args (value can be
+ *        F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NOT_NULL,
+ *        F_GV11B_L2_FLUSH_PASS_BAR1_BIND_NULL, F_GV11B_L2_FLUSH_FB_FLUSH_FAIL,
+ *        F_GV11B_L2_FLUSH_L2_FLUSH_FAIL, F_GV11B_L2_FLUSH_TLB_INVALIDATE_FAIL,
+ *        F_GV11B_L2_FLUSH_FB_FLUSH2_FAIL)
+ *
+ * Steps:
+ * - Invoke L2 flush command
+ * - Test L2 flush with various scenarios as below:
+ *   - fb_flush is successful or fails
+ *   - l2_flush passes or fails
+ *   - bar1_bind is populated or not populated
+ *   - tlb_invalidate passes or fails
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_l2_flush(struct unit_module *m, struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_env_clean_flush_gv11b_fusa
+ *
+ * Description: Cleanup test environment
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Destroy memory and VMs initialized for the test.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_clean_flush_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+	void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_CACHE_FLUSH_GV11B_FUSA_H */

userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = gmmu-gk20a-fusa.o
+MODULE = gmmu-gk20a-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gk20a-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gk20a-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/gmmu.h>
+#include "hal/mm/gmmu/gmmu_gk20a.h"
+
+#include "gmmu-gk20a-fusa.h"
+
+int test_gk20a_get_pde_pgsz(struct unit_module *m, struct gk20a *g, void *args)
+{
+	struct gk20a_mmu_level l;
+	struct nvgpu_gmmu_pd pd;
+	u32 ret_pgsz;
+	int ret = UNIT_FAIL;
+
+	ret_pgsz = gk20a_get_pde_pgsz(g, &l, &pd, 0U);
+	unit_assert(ret_pgsz == GMMU_PAGE_SIZE_SMALL, goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s pde_pgsz != GMMU_PAGE_SIZE_SMALL as expected\n",
+				__func__);
+	}
+
+	return ret;
+}
+
+int test_gk20a_get_pte_pgsz(struct unit_module *m, struct gk20a *g, void *args)
+{
+	struct gk20a_mmu_level l;
+	struct nvgpu_gmmu_pd pd;
+	u32 ret_pgsz;
+	int ret = UNIT_FAIL;
+
+	ret_pgsz = gk20a_get_pte_pgsz(g, &l, &pd, 0U);
+	unit_assert(ret_pgsz == GMMU_NR_PAGE_SIZES, goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s pte_pgsz != GMMU_NR_PAGE_SIZES as expected\n",
+				__func__);
+	}
+
+	return ret;
+}
+
+struct unit_module_test mm_gmmu_gk20a_fusa_tests[] = {
+	UNIT_TEST(pde_pgsz, test_gk20a_get_pde_pgsz, NULL, 0),
+	UNIT_TEST(pte_pgsz, test_gk20a_get_pte_pgsz, NULL, 0),
+};
+
+UNIT_MODULE(gmmu_gk20a_fusa, mm_gmmu_gk20a_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/gmmu/gmmu_gk20a_fusa/gmmu-gk20a-fusa.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_GMMU_GMMU_GK20A_FUSA_H
+#define UNIT_MM_HAL_GMMU_GMMU_GK20A_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gk20a_fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.gmmu.gmmu_gk20a_fusa
+ */
+
+/**
+ * Test specification for: test_gk20a_get_pde_pgsz
+ *
+ * Description: Test PDE page size
+ *
+ * Test Type: Feature
+ *
+ * Targets: gk20a_get_pde_pgsz
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check PDE page size value using the get_pgsz API
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gk20a_get_pde_pgsz(struct unit_module *m, struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gk20a_get_pte_pgsz
+ *
+ * Description: Test PTE page size
+ *
+ * Test Type: Feature
+ *
+ * Targets: gk20a_get_pte_pgsz
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check PTE page size value using the get_pgsz API
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gk20a_get_pte_pgsz(struct unit_module *m, struct gk20a *g, void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_GMMU_GMMU_GK20A_FUSA_H */

userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = gmmu-gm20b-fusa.o
+MODULE = gmmu-gm20b-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gm20b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gm20b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+
+#include "hal/mm/gmmu/gmmu_gm20b.h"
+
+#include "gmmu-gm20b-fusa.h"
+
+
+int test_gm20b_mm_get_big_page_sizes(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	u32 ret_pgsz;
+	int ret = UNIT_FAIL;
+
+	ret_pgsz = gm20b_mm_get_big_page_sizes();
+	unit_assert(ret_pgsz == (SZ_64K | SZ_128K), goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s pde_pgsz != GMMU_PAGE_SIZE_SMALL as expected\n",
+				__func__);
+	}
+
+	return ret;
+}
+
+struct unit_module_test mm_gmmu_gm20b_fusa_tests[] = {
+	UNIT_TEST(get_big_pgsz, test_gm20b_mm_get_big_page_sizes, NULL, 0),
+};
+
+UNIT_MODULE(gmmu_gm20b_fusa, mm_gmmu_gm20b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/gmmu/gmmu_gm20b_fusa/gmmu-gm20b-fusa.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_GMMU_GMMU_GM20B_FUSA_H
+#define UNIT_MM_HAL_GMMU_GMMU_GM20B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gm20b_fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.gmmu.gmmu_gm20b_fusa
+ */
+
+/**
+ * Test specification for: test_gm20b_mm_get_big_page_sizes
+ *
+ * Description: Test big page size
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_gmmu.get_big_page_sizes, gm20b_mm_get_big_page_sizes
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check big page size value
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gm20b_mm_get_big_page_sizes(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_GMMU_GMMU_GM20B_FUSA_H */

userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = gmmu-gp10b-fusa.o
+MODULE = gmmu-gp10b-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gp10b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gp10b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.c

@@ -0,0 +1,552 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/vm.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
+
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+
+#include "gmmu-gp10b-fusa.h"
+
+static u32 max_page_table_levels;
+static const struct gk20a_mmu_level *mmu_level;
+
+int test_gp10b_mm_get_default_big_page_size(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	u32 ret_pgsz;
+	int ret = UNIT_FAIL;
+
+	ret_pgsz = nvgpu_gmmu_default_big_page_size();
+	unit_assert(ret_pgsz == U32(SZ_64K), goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: big page size != 64K as expected\n", __func__);
+	}
+
+	return ret;
+}
+
+int test_gp10b_mm_get_iommu_bit(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	u32 ret_bit;
+	int ret = UNIT_FAIL;
+
+	ret_bit = gp10b_mm_get_iommu_bit(g);
+	unit_assert(ret_bit == 36U, goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: iommu bit != 36 as expected\n", __func__);
+	}
+
+	return ret;
+}
+
+int test_gp10b_get_max_page_table_levels(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+
+	max_page_table_levels = gp10b_get_max_page_table_levels(g);
+	unit_assert(max_page_table_levels == 5U, goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: max page table levels != 5 as expected\n",
+								__func__);
+	}
+
+	return ret;
+}
+
+int test_gp10b_mm_get_mmu_levels(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	const struct gk20a_mmu_level *l;
+	u32 i;
+
+	l = gp10b_mm_get_mmu_levels(g, SZ_64K);
+
+	for (i = 0; i < max_page_table_levels; i++) {
+		unit_assert((l->update_entry != NULL), goto done);
+		l++;
+	}
+	unit_assert(l->update_entry == NULL, goto done);
+
+	/* If get mmu_levels is successful, copy mmu_levels for future use */
+	mmu_level = gp10b_mm_get_mmu_levels(g, SZ_64K);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: max page table levels != 5 as expected\n",
+								__func__);
+	}
+
+	return ret;
+}
+
+int test_update_gmmu_pde3_locked(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	struct vm_gk20a vm;
+	struct nvgpu_gmmu_pd pd;
+	struct nvgpu_gmmu_attrs attrs;
+	const struct gk20a_mmu_level *l = mmu_level;
+	u64 vaddr, size = SZ_4K;
+	u32 data = 0U;
+	u32 *data_ptr = NULL;
+
+	unit_assert(l != NULL, goto done);
+
+	unit_assert(g->mm.pd_cache == NULL, goto done);
+
+	vm.mm = &g->mm;
+	vm.mm->g = g;
+	err = nvgpu_pd_cache_init(g);
+	unit_assert(err == 0, goto done);
+
+	err = nvgpu_pd_alloc(&vm, &pd, size);
+	unit_assert(err == 0, goto done);
+
+	vaddr = nvgpu_pd_gpu_addr(g, &pd);
+	unit_assert(vaddr != 0ULL, goto done);
+
+	pd.entries = (struct nvgpu_gmmu_pd *) nvgpu_kzalloc(g,
+						sizeof(struct nvgpu_gmmu_pd));
+	unit_assert(pd.entries != NULL, goto done);
+
+	pd.entries->mem = (struct nvgpu_mem *) nvgpu_kzalloc(g,
+						sizeof(struct nvgpu_mem));
+	unit_assert(pd.entries->mem != NULL, goto done);
+
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
+	pd.entries->mem->aperture = APERTURE_SYSMEM;
+
+	l[0].update_entry(&vm, l, &pd, 0U, vaddr, size, &attrs);
+
+	/* Compute data written to pd->mem */
+	/* pd.entries->mem is SYSMEM with HONORS_APERTURE */
+	data_ptr = pd.mem->cpu_va;
+
+	data |= gmmu_new_pde_aperture_sys_mem_ncoh_f();
+	data |= gmmu_new_pde_address_sys_f(size >>
+						gmmu_new_pde_address_shift_v());
+	data |= gmmu_new_pde_vol_true_f();
+
+	unit_assert(data == data_ptr[0], goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed\n", __func__);
+	}
+	if (pd.entries->mem != NULL) {
+		nvgpu_kfree(g, pd.entries->mem);
+	}
+	if (pd.entries != NULL) {
+		nvgpu_kfree(g, pd.entries);
+	}
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
+	nvgpu_pd_free(&vm, &pd);
+	nvgpu_pd_cache_fini(g);
+	return ret;
+}
+
+#define F_UPDATE_GMMU_PDE0_SMALL_PAGE		0ULL
+#define F_UPDATE_GMMU_PDE0_BIG_PAGE		1ULL
+
+static const char *f_gmmu_pde0_locked[] = {
+	"gmmu_small_page_size",
+	"gmmu_big_page_size",
+};
+
+int test_update_gmmu_pde0_locked(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	u64 branch = (u64)args;
+	struct vm_gk20a vm;
+	struct nvgpu_gmmu_pd pd;
+	struct nvgpu_gmmu_attrs attrs;
+	const struct gk20a_mmu_level *l = mmu_level;
+	u64 vaddr, size = SZ_4K;
+	u32 data = 0U;
+	u32 *data_ptr = NULL;
+
+	unit_assert(l != NULL, goto done);
+
+	unit_assert(g->mm.pd_cache == NULL, goto done);
+
+	vm.mm = &g->mm;
+	err = nvgpu_pd_cache_init(g);
+	unit_assert(err == 0, goto done);
+
+	err = nvgpu_pd_alloc(&vm, &pd, size);
+	unit_assert(err == 0, goto done);
+
+	vaddr = nvgpu_pd_gpu_addr(g, &pd);
+	unit_assert(vaddr != 0ULL, goto done);
+
+	pd.entries = (struct nvgpu_gmmu_pd *) nvgpu_kzalloc(g,
+						sizeof(struct nvgpu_gmmu_pd));
+	unit_assert(pd.entries != NULL, goto done);
+
+	pd.entries->mem = (struct nvgpu_mem *) nvgpu_kzalloc(g,
+						sizeof(struct nvgpu_mem));
+	unit_assert(pd.entries->mem != NULL, goto done);
+
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
+	pd.entries->mem->aperture = APERTURE_SYSMEM;
+	attrs.pgsz = branch == F_UPDATE_GMMU_PDE0_SMALL_PAGE ?
+			GMMU_PAGE_SIZE_SMALL : GMMU_PAGE_SIZE_BIG;
+
+	l[3].update_entry(&vm, l, &pd, 0U, vaddr, size, &attrs);
+
+	/* Compute data written to pd->mem */
+	/* pd.entries->mem is SYSMEM with HONORS_APERTURE */
+	data_ptr = pd.mem->cpu_va;
+
+	if (branch == F_UPDATE_GMMU_PDE0_SMALL_PAGE) {
+		data |= gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f();
+		data |= gmmu_new_dual_pde_address_small_sys_f(size >>
+					gmmu_new_dual_pde_address_shift_v());
+		data |= gmmu_new_dual_pde_vol_small_true_f();
+
+		unit_assert(data == data_ptr[2], goto done);
+	} else {
+		data |= gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f();
+		data |= gmmu_new_dual_pde_address_big_sys_f(size >>
+				gmmu_new_dual_pde_address_big_shift_v());
+		data |= gmmu_new_dual_pde_vol_big_true_f();
+
+		unit_assert(data == data_ptr[0], goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_gmmu_pde0_locked[branch]);
+	}
+	if (pd.entries->mem != NULL) {
+		nvgpu_kfree(g, pd.entries->mem);
+	}
+	if (pd.entries != NULL) {
+		nvgpu_kfree(g, pd.entries);
+	}
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
+	nvgpu_pd_free(&vm, &pd);
+	nvgpu_pd_cache_fini(g);
+	return ret;
+}
+
+#define F_ATTRS_PRIV			0x1ULL
+#define F_ATTRS_READ_ONLY		0x2ULL
+#define F_ATTRS_VALID			0x4ULL
+#define F_ATTRS_CACHEABLE		0x8ULL
+#define F_ATTRS_APERTURE_VIDMEM		0x10ULL
+#define F_PLATFORM_ATOMIC		0x20ULL
+#define F_UPDATE_PTE			0x40ULL
+#define F_UPDATE_PTE_SPARSE		0x80ULL
+
+#define F_UPDATE_PTE_PHYS_ADDR_ZERO		0x00ULL
+/* F_UPDATE_PTE */
+#define F_UPDATE_PTE_DEFAULT			0x40ULL
+/* F_UPDATE_PTE | F_ATTRS_PRIV | F_ATTRS_READ_ONLY */
+#define F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY	0x43ULL
+/* F_UPDATE_PTE | F_ATTRS_VALID */
+#define F_UPDATE_PTE_ATTRS_VALID		0x44ULL
+/* F_UPDATE_PTE | F_ATTRS_CACHEABLE */
+#define F_UPDATE_PTE_ATTRS_CACHEABLE		0x48ULL
+/* F_UPDATE_PTE | F_ATTRS_APERTURE_VIDMEM */
+#define F_UPDATE_PTE_ATTRS_VIDMEM		0x50ULL
+/* F_UPDATE_PTE | F_PLATFORM_ATOMIC */
+#define F_UPDATE_PTE_PLATFORM_ATOMIC		0x60ULL
+
+static const char *f_gmmu_pte_locked[] = {
+	[F_UPDATE_PTE_DEFAULT] = "update_pte_default",
+	[F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY] = "update_pte_attrs_priv_read_only",
+	[F_UPDATE_PTE_ATTRS_VALID] = "update_pte_attrs_valid",
+	[F_UPDATE_PTE_ATTRS_CACHEABLE] = "update_pte_attrs_cacheable",
+	[F_UPDATE_PTE_ATTRS_VIDMEM] = "update_pte_attrs_vidmem",
+	[F_UPDATE_PTE_PLATFORM_ATOMIC] = "update_pte_platform_atomic",
+	[F_UPDATE_PTE_SPARSE] = "update_pte_sparse",
+};
+
+int test_update_gmmu_pte_locked(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	u64 branch = (u64)args;
+	struct vm_gk20a vm;
+	struct nvgpu_gmmu_pd pd;
+	struct nvgpu_gmmu_attrs attrs = {0};
+	const struct gk20a_mmu_level *l = mmu_level;
+	u64 vaddr, size = SZ_4K, paddr = 0;
+	u32 data = 0U;
+	u32 *data_ptr = NULL;
+
+	unit_assert(l != NULL, goto done);
+
+	unit_assert(g->mm.pd_cache == NULL, goto done);
+
+	vm.mm = &g->mm;
+	err = nvgpu_pd_cache_init(g);
+	unit_assert(err == 0, goto done);
+
+	err = nvgpu_pd_alloc(&vm, &pd, size);
+	unit_assert(err == 0, goto done);
+
+	vaddr = nvgpu_pd_gpu_addr(g, &pd);
+	unit_assert(vaddr != 0ULL, goto done);
+
+	pd.entries = (struct nvgpu_gmmu_pd *) nvgpu_kzalloc(g,
+						sizeof(struct nvgpu_gmmu_pd));
+	unit_assert(pd.entries != NULL, goto done);
+
+	pd.entries->mem = (struct nvgpu_mem *) nvgpu_kzalloc(g,
+						sizeof(struct nvgpu_mem));
+	unit_assert(pd.entries->mem != NULL, goto done);
+
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
+	pd.entries->mem->aperture = APERTURE_SYSMEM;
+	attrs.pgsz = GMMU_PAGE_SIZE_SMALL;
+	vm.gmmu_page_sizes[GMMU_PAGE_SIZE_SMALL] = SZ_4K;
+
+	paddr = branch & F_UPDATE_PTE ? size : 0ULL;
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC,
+				(branch & F_PLATFORM_ATOMIC ? true : false));
+
+	attrs.platform_atomic = branch & F_PLATFORM_ATOMIC ? true : false;
+	attrs.aperture = branch & F_ATTRS_APERTURE_VIDMEM ?
+				APERTURE_VIDMEM : APERTURE_SYSMEM;
+	attrs.priv = branch & F_ATTRS_PRIV ? true : false;
+	attrs.rw_flag = branch & F_ATTRS_READ_ONLY ?
+			gk20a_mem_flag_read_only : gk20a_mem_flag_none;
+	attrs.valid = branch & F_ATTRS_VALID ? true : false;
+	attrs.cacheable = branch & F_ATTRS_CACHEABLE ? true : false;
+	attrs.sparse = branch & F_UPDATE_PTE_SPARSE ? true : false;
+
+	l[4].update_entry(&vm, l, &pd, 0U, vaddr, paddr, &attrs);
+
+	/* Compute data written to pd->mem */
+	/* pd.entries->mem is SYSMEM with HONORS_APERTURE */
+	data_ptr = pd.mem->cpu_va;
+
+	if (branch & F_UPDATE_PTE) {
+		data |= branch & F_ATTRS_APERTURE_VIDMEM ?
+			gmmu_new_pte_address_vid_f(paddr >>
+					gmmu_new_pte_address_shift_v()) :
+			gmmu_new_pte_address_sys_f(paddr >>
+					gmmu_new_pte_address_shift_v());
+		data |= branch & F_PLATFORM_ATOMIC ?
+			gmmu_new_pte_aperture_sys_mem_coh_f() :
+			branch & F_ATTRS_APERTURE_VIDMEM ?
+				gmmu_new_pte_aperture_video_memory_f() :
+				gmmu_new_pte_aperture_sys_mem_ncoh_f();
+		data |= branch & F_ATTRS_VALID ? gmmu_new_pte_valid_true_f() :
+						gmmu_new_pte_valid_false_f();
+		data |= branch & F_ATTRS_PRIV ?
+					gmmu_new_pte_privilege_true_f() : 0U;
+		data |= branch & F_ATTRS_READ_ONLY ?
+					gmmu_new_pte_read_only_true_f() : 0U;
+
+		if (!(branch & F_ATTRS_CACHEABLE)) {
+			data |= branch & F_ATTRS_VALID ?
+						gmmu_new_pte_vol_true_f() :
+						gmmu_new_pte_read_only_true_f();
+		}
+	} else if (branch & F_UPDATE_PTE_SPARSE) {
+		data = gmmu_new_pte_valid_false_f();
+		data |= gmmu_new_pte_vol_true_f();
+	}
+
+	unit_assert(data == data_ptr[0], goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_gmmu_pte_locked[branch]);
+	}
+	if (pd.entries->mem != NULL) {
+		nvgpu_kfree(g, pd.entries->mem);
+	}
+	if (pd.entries != NULL) {
+		nvgpu_kfree(g, pd.entries);
+	}
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
+	nvgpu_pd_free(&vm, &pd);
+	nvgpu_pd_cache_fini(g);
+	return ret;
+}
+
+#define F_PDE_V0_VALUE_SET			0x1ULL
+#define F_PDE_V1_VALUE_SET			0x2ULL
+#define F_PDE_V2_VALUE_SET			0x4ULL
+#define F_PDE_V3_VALUE_SET			0x8ULL
+
+#define F_PDE_BIG_PAGE_APERTURE_SET_ONLY	0x01ULL
+#define F_PDE_BIG_PAGE_APERTURE_ADDR_SET	0x03ULL
+#define F_PDE_SMALL_PAGE_APERTURE_SET_ONLY	0x04ULL
+#define F_PDE_SMALL_PAGE_APERTURE_ADDR_SET	0x0CULL
+#define F_PDE_SMALL_BIG_SET			0x0FULL
+#define F_PDE0_PGSZ_MEM_NULL			0x10ULL
+
+static const char *f_get_pde0_pgsz[] = {
+	[F_PDE_BIG_PAGE_APERTURE_SET_ONLY] =
+				"get_pde0_pgsz_big_page_only_aperture_set",
+	[F_PDE_BIG_PAGE_APERTURE_ADDR_SET] =
+				"get_pde0_pgsz_big_page_aperture_addr_set",
+	[F_PDE_SMALL_PAGE_APERTURE_SET_ONLY] =
+				"get_pde0_pgsz_small_page_only_aperture_set",
+	[F_PDE_SMALL_PAGE_APERTURE_ADDR_SET] =
+				"get_pde0_pgsz_small_page_aperture_addr_set",
+	[F_PDE_SMALL_BIG_SET] = "get_pde0_pgsz_small_big_set",
+	[F_PDE0_PGSZ_MEM_NULL] = "get_pde0_pgsz_mem_null",
+};
+
+int test_gp10b_get_pde0_pgsz(struct unit_module *m, struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	u64 branch = (u64)args;
+	struct vm_gk20a vm;
+	struct nvgpu_gmmu_pd pd;
+	const struct gk20a_mmu_level *l = mmu_level;
+	u64 vaddr, size = SZ_4K;
+	u32 *data;
+	u32 ret_pgsz;
+	struct nvgpu_mem *tmp_mem_ptr = NULL;
+
+	unit_assert(l != NULL, goto done);
+
+	unit_assert(g->mm.pd_cache == NULL, goto done);
+
+	vm.mm = &g->mm;
+	err = nvgpu_pd_cache_init(g);
+	unit_assert(err == 0, goto done);
+
+	err = nvgpu_pd_alloc(&vm, &pd, size);
+	unit_assert(err == 0, goto done);
+
+	vaddr = nvgpu_pd_gpu_addr(g, &pd);
+	unit_assert(vaddr != 0ULL, goto done);
+
+	if (branch & F_PDE0_PGSZ_MEM_NULL) {
+		tmp_mem_ptr = pd.mem;
+		pd.mem = NULL;
+	} else {
+		data = pd.mem->cpu_va;
+
+		data[0] = branch & F_PDE_V0_VALUE_SET ?
+			(gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() |
+			gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() |
+			gmmu_new_dual_pde_aperture_big_video_memory_f()) : 0U;
+		data[1] = branch & F_PDE_V1_VALUE_SET ? 1U : 0U;
+		data[2] = branch & F_PDE_V2_VALUE_SET ?
+			(gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() |
+			gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() |
+			gmmu_new_dual_pde_aperture_small_video_memory_f()) : 0U;
+		data[3] = branch & F_PDE_V3_VALUE_SET ? 1U : 0U;
+	}
+
+	ret_pgsz = l[3].get_pgsz(g, l, &pd, 0U);
+
+	if (branch == F_PDE_BIG_PAGE_APERTURE_ADDR_SET) {
+		unit_assert(ret_pgsz == GMMU_PAGE_SIZE_BIG, goto done);
+	} else if (branch == F_PDE_SMALL_PAGE_APERTURE_ADDR_SET) {
+		unit_assert(ret_pgsz == GMMU_PAGE_SIZE_SMALL, goto done);
+	} else {
+		unit_assert(ret_pgsz == GMMU_NR_PAGE_SIZES, goto done);
+	}
+
+	if (branch & F_PDE0_PGSZ_MEM_NULL) {
+		pd.mem = tmp_mem_ptr;
+	}
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_get_pde0_pgsz[branch]);
+	}
+	nvgpu_pd_free(&vm, &pd);
+	nvgpu_pd_cache_fini(g);
+	return ret;
+}
+
+struct unit_module_test mm_gmmu_gp10b_fusa_tests[] = {
+	UNIT_TEST(big_pgsz, test_gp10b_mm_get_default_big_page_size, NULL, 0),
+	UNIT_TEST(iommu_bit, test_gp10b_mm_get_iommu_bit, NULL, 0),
+	UNIT_TEST(max_page_table_levels, test_gp10b_get_max_page_table_levels, NULL, 0),
+	UNIT_TEST(mmu_levels, test_gp10b_mm_get_mmu_levels, NULL, 0),
+	UNIT_TEST(update_gmmu_pde3_locked, test_update_gmmu_pde3_locked, NULL, 0),
+	UNIT_TEST(update_gmmu_pde0_locked_s0, test_update_gmmu_pde0_locked, (void *)F_UPDATE_GMMU_PDE0_SMALL_PAGE, 0),
+	UNIT_TEST(update_gmmu_pde0_locked_s1, test_update_gmmu_pde0_locked, (void *)F_UPDATE_GMMU_PDE0_BIG_PAGE, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s0, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_PHYS_ADDR_ZERO, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s1, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_DEFAULT, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s2, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s3, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_VALID, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s4, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_CACHEABLE, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s5, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_ATTRS_VIDMEM, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s6, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_PLATFORM_ATOMIC, 0),
+	UNIT_TEST(update_gmmu_pte_locked_s7, test_update_gmmu_pte_locked, (void *)F_UPDATE_PTE_SPARSE, 0),
+	UNIT_TEST(gp10b_get_pde0_pgsz_s0, test_gp10b_get_pde0_pgsz, (void *)F_PDE_BIG_PAGE_APERTURE_SET_ONLY, 0),
+	UNIT_TEST(gp10b_get_pde0_pgsz_s1, test_gp10b_get_pde0_pgsz, (void *)F_PDE_BIG_PAGE_APERTURE_ADDR_SET, 0),
+	UNIT_TEST(gp10b_get_pde0_pgsz_s2, test_gp10b_get_pde0_pgsz, (void *)F_PDE_SMALL_PAGE_APERTURE_SET_ONLY, 0),
+	UNIT_TEST(gp10b_get_pde0_pgsz_s3, test_gp10b_get_pde0_pgsz, (void *)F_PDE_SMALL_PAGE_APERTURE_ADDR_SET, 0),
+	UNIT_TEST(gp10b_get_pde0_pgsz_s4, test_gp10b_get_pde0_pgsz, (void *)F_PDE_SMALL_BIG_SET, 0),
+	UNIT_TEST(gp10b_get_pde0_pgsz_s5, test_gp10b_get_pde0_pgsz, (void *)F_PDE0_PGSZ_MEM_NULL, 0),
+};
+
+UNIT_MODULE(gmmu_gp10b_fusa, mm_gmmu_gp10b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/gmmu/gmmu_gp10b_fusa/gmmu-gp10b-fusa.h

@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_GMMU_GMMU_GP10B_FUSA_H
+#define UNIT_MM_HAL_GMMU_GMMU_GP10B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gp10b_fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.gmmu.gmmu_gp10b_fusa
+ */
+
+/**
+ * Test specification for: test_gp10b_mm_get_default_big_page_size
+ *
+ * Description: Test big page size
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_gmmu.get_default_big_page_size,
+ * nvgpu_gmmu_default_big_page_size
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Check big page size value and confirm that size is 64K.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gp10b_mm_get_default_big_page_size(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gp10b_mm_get_iommu_bit
+ *
+ * Description: Test IOMMU bit number
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_gmmu.get_iommu_bit, gp10b_mm_get_iommu_bit
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Check iommu bit is equal to 36.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gp10b_mm_get_iommu_bit(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_gp10b_get_max_page_table_levels
+ *
+ * Description: Test max page table levels
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_gmmu.get_max_page_table_levels,
+ * gp10b_get_max_page_table_levels
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Check max page table levels is 5.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gp10b_get_max_page_table_levels(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gp10b_mm_get_mmu_levels
+ *
+ * Description: Test mmu_levels structure
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_gmmu.get_mmu_levels, gp10b_mm_get_mmu_levels
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Copy mmu_levels structure and validate struct using update_entry pointer.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gp10b_mm_get_mmu_levels(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_update_gmmu_pde3_locked
+ *
+ * Description: Test mmu_levels update entry function
+ *
+ * Test Type: Feature
+ *
+ * Targets: update_gmmu_pde3_locked, pte_dbg_print
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Update gmmu pde3 for given physical address.
+ * - Check if data written to memory is as expected.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_update_gmmu_pde3_locked(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_update_gmmu_pde0_locked
+ *
+ * Description: Test mmu_level 3 update entry function
+ *
+ * Test Type: Feature
+ *
+ * Targets: update_gmmu_pde0_locked, pte_dbg_print
+ *
+ * Input: args (value can be F_UPDATE_GMMU_PDE0_SMALL_PAGE or
+ *        F_UPDATE_GMMU_PDE0_BIG_PAGE)
+ *
+ * Steps:
+ * - Update gmmu pde3 for given physical address.
+ * - For big and small page size, check data written to memory.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_update_gmmu_pde0_locked(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_update_gmmu_pte_locked
+ *
+ * Description: Test mmu_level 4 update entry function
+ *
+ * Test Type: Feature
+ *
+ * Targets: update_gmmu_pte_locked, update_pte, update_pte_sparse,
+ *          gmmu_aperture_mask
+ *
+ * Input: args (value can be F_UPDATE_PTE_PHYS_ADDR_ZERO, F_UPDATE_PTE_DEFAULT,
+ *        F_UPDATE_PTE_ATTRS_PRIV_READ_ONLY, F_UPDATE_PTE_ATTRS_VALID,
+ *        F_UPDATE_PTE_ATTRS_CACHEABLE, F_UPDATE_PTE_ATTRS_VIDMEM,
+ *        F_UPDATE_PTE_PLATFORM_ATOMIC or F_UPDATE_PTE_SPARSE)
+ *
+ * Steps:
+ * - Update gmmu pte for given physical address.
+ * - Check data written to pd mem for various scenarios such as cacheable GMMU
+ *   mapping, priviledged mapping, read only address, etc.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_update_gmmu_pte_locked(struct unit_module *m,
+						struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gp10b_get_pde0_pgsz
+ *
+ * Description: Test GMMU level 3 page size function
+ *
+ * Test Type: Feature
+ *
+ * Targets: gp10b_get_pde0_pgsz
+ *
+ * Input: args (value can be F_PDE_BIG_PAGE_APERTURE_SET_ONLY,
+ *        F_PDE_BIG_PAGE_APERTURE_ADDR_SET, F_PDE_SMALL_PAGE_APERTURE_SET_ONLY,
+ *        F_PDE_SMALL_PAGE_APERTURE_ADDR_SET, F_PDE_SMALL_BIG_SET or
+ *        F_PDE0_PGSZ_MEM_NULL)
+ *
+ * Steps:
+ * - Check pde0 page size for given aperture values
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gp10b_get_pde0_pgsz(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_GMMU_GMMU_GP10B_FUSA_H */

userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = gmmu-gv11b-fusa.o
+MODULE = gmmu-gv11b-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=gmmu-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.c

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/gmmu.h>
+
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/gmmu/gmmu_gv11b.h"
+
+#include "gmmu-gv11b-fusa.h"
+
+#define F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL	0
+#define F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE	1
+#define F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE	2
+
+int test_gv11b_gpu_phys_addr(struct unit_module *m, struct gk20a *g, void *args)
+{
+	struct gpu_ops gops = g->ops;
+	struct nvgpu_gmmu_attrs attrs = {0};
+	struct nvgpu_gmmu_attrs *attrs_ptr;
+	u64 phys = BIT(10);
+	u64 ret_phys;
+	u64 branch = (u64)args;
+	int ret = UNIT_FAIL;
+
+	g->ops.mm.gmmu.get_iommu_bit = gp10b_mm_get_iommu_bit;
+
+	attrs_ptr = branch == F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL ?
+			NULL : &attrs;
+
+	attrs.l3_alloc = branch == F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE ?
+			false : true;
+
+	ret_phys = gv11b_gpu_phys_addr(g, attrs_ptr, phys);
+
+	if (branch == F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE) {
+		unit_assert(ret_phys == (phys |
+			BIT64(g->ops.mm.gmmu.get_iommu_bit(g))),
+			goto done);
+	} else {
+		unit_assert(ret_phys == phys, goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s pde_pgsz != GMMU_PAGE_SIZE_SMALL as expected\n",
+				__func__);
+	}
+
+	g->ops = gops;
+	return ret;
+}
+
+struct unit_module_test mm_gmmu_gv11b_fusa_tests[] = {
+	UNIT_TEST(gpu_phys_addr_s0, test_gv11b_gpu_phys_addr, (void *)F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL, 0),
+	UNIT_TEST(gpu_phys_addr_s1, test_gv11b_gpu_phys_addr, (void *)F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE, 0),
+	UNIT_TEST(gpu_phys_addr_s2, test_gv11b_gpu_phys_addr, (void *)F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE, 0),
+};
+
+UNIT_MODULE(gmmu_gv11b_fusa, mm_gmmu_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/gmmu/gmmu_gv11b_fusa/gmmu-gv11b-fusa.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_GMMU_GMMU_GV11B_FUSA_H
+#define UNIT_MM_HAL_GMMU_GMMU_GV11B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-gmmu-gmmu_gv11b_fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.gmmu.gmmu_gv11b_fusa
+ */
+
+/**
+ * Test specification for: test_gv11b_gpu_phys_addr
+ *
+ * Description: Test PTE page size
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_gmmu.gpu_phys_addr, gv11b_gpu_phys_addr
+ *
+ * Input: args (value can be F_GV11B_GPU_PHYS_ADDR_GMMU_ATTRS_NULL,
+ *        F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_FALSE or
+ *        F_GV11B_GPU_PHYS_ADDR_L3_ALLOC_TRUE)
+ *
+ * Steps:
+ * - Check PTE page size value using the get_pgsz API
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_gpu_phys_addr(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_GMMU_GMMU_GV11B_FUSA_H */

userspace/units/mm/hal/gp10b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = mm-gp10b-fusa.o
+MODULE = mm-gp10b-fusa
+
+include ../../../Makefile.units

userspace/units/mm/hal/gp10b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=mm-gp10b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gp10b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=mm-gp10b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.c

@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/vm.h>
+
+#include "os/posix/os_posix.h"
+
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/mc/mc_gp10b.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
+
+#include <nvgpu/posix/posix-fault-injection.h>
+#include <nvgpu/posix/dma.h>
+
+#include "mm-gp10b-fusa.h"
+
+/*
+ * Write callback (for all nvgpu_writel calls).
+ */
+static void writel_access_reg_fn(struct gk20a *g,
+			     struct nvgpu_reg_access *access)
+{
+	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+}
+
+/*
+ * Read callback, similar to the write callback above.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+			    struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+/*
+ * Define all the callbacks to be used during the test. Typically all
+ * write operations use the same callback, likewise for all read operations.
+ */
+static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+};
+
+static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
+{
+	if (is_iGPU) {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	} else {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
+	}
+}
+
+static int init_mm(struct unit_module *m, struct gk20a *g)
+{
+	u64 low_hole, aperture_size;
+	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
+	struct mm_gk20a *mm = &g->mm;
+	int err;
+
+	p->mm_is_iommuable = true;
+
+	/* Minimum HALs for page_table */
+	memset(&g->ops.bus, 0, sizeof(g->ops.bus));
+	memset(&g->ops.fb, 0, sizeof(g->ops.fb));
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.ramin.init_pdb = gv11b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+	g->ops.mm.gmmu.get_default_big_page_size =
+					nvgpu_gmmu_default_big_page_size;
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
+	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
+	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
+	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
+	g->ops.mm.mmu_fault.info_mem_destroy =
+					gv11b_mm_mmu_fault_info_mem_destroy;
+	g->ops.mc.intr_stall_unit_config = mc_gp10b_intr_stall_unit_config;
+
+	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
+
+	/* Register space: FB_MMU */
+	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
+		unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
+	}
+
+	/*
+	 * Initialize VM space for system memory to be used throughout this
+	 * unit module.
+	 * Values below are similar to those used in nvgpu_init_system_vm()
+	 */
+	low_hole = SZ_4K * 16UL;
+	aperture_size = GK20A_PMU_VA_SIZE;
+	mm->pmu.aperture_size = GK20A_PMU_VA_SIZE;
+
+	mm->pmu.vm = nvgpu_vm_init(g,
+				   g->ops.mm.gmmu.get_default_big_page_size(),
+				   low_hole,
+				   0ULL,
+				   nvgpu_safe_sub_u64(aperture_size, low_hole),
+				   0ULL,
+				   true,
+				   false,
+				   false,
+				   "system");
+	if (mm->pmu.vm == NULL) {
+		unit_return_fail(m, "'system' nvgpu_vm_init failed\n");
+	}
+
+	/*
+	 * This initialization will make sure that correct aperture mask
+	 * is returned */
+	g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM;
+	g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
+
+	/* Init MM H/W */
+	err = g->ops.mm.setup_hw(g);
+	if (err != 0) {
+		unit_return_fail(m, "init_mm_setup_hw failed code=%d\n", err);
+	}
+
+	return UNIT_SUCCESS;
+}
+
+int test_env_init_mm_gp10b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+
+	init_platform(m, g, true);
+
+	if (init_mm(m, g) != 0) {
+		unit_return_fail(m, "nvgpu_init_mm_support failed\n");
+	}
+
+	return UNIT_SUCCESS;
+}
+
+#define F_INIT_BAR2_VM_DEFAULT			0ULL
+#define F_INIT_BAR2_VM_INIT_VM_FAIL		1ULL
+#define F_INIT_BAR2_VM_ALLOC_INST_BLOCK_FAIL	2ULL
+
+const char *m_init_bar2_vm_str[] = {
+	"default_input",
+	"vm_init_fail",
+	"alloc_inst_block_fail",
+};
+
+int test_gp10b_mm_init_bar2_vm(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int err;
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+	u64 fail = F_INIT_BAR2_VM_INIT_VM_FAIL |
+			F_INIT_BAR2_VM_ALLOC_INST_BLOCK_FAIL;
+	struct nvgpu_posix_fault_inj *kmem_fi =
+					nvgpu_kmem_get_fault_injection();
+	struct nvgpu_posix_fault_inj *dma_fi =
+					nvgpu_dma_alloc_get_fault_injection();
+
+	if ((branch & F_INIT_BAR2_VM_INIT_VM_FAIL) != 0) {
+		nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
+	}
+
+	if ((branch & F_INIT_BAR2_VM_ALLOC_INST_BLOCK_FAIL) != 0) {
+		nvgpu_posix_enable_fault_injection(dma_fi, true, 1);
+	}
+
+	err = gp10b_mm_init_bar2_vm(g);
+
+	if (branch & fail) {
+		nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
+		nvgpu_posix_enable_fault_injection(dma_fi, false, 0);
+		unit_assert(err != 0, goto done);
+	} else {
+		unit_assert(err == 0, goto done);
+		gp10b_mm_remove_bar2_vm(g);
+	}
+
+	ret = UNIT_SUCCESS;
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed at %s\n", __func__,
+						m_init_bar2_vm_str[branch]);
+	}
+	return ret;
+}
+
+int test_env_clean_mm_gp10b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+	g->ops.mm.mmu_fault.info_mem_destroy(g);
+	nvgpu_vm_put(g->mm.pmu.vm);
+
+	return UNIT_SUCCESS;
+}
+
+struct unit_module_test mm_gp10b_fusa_tests[] = {
+	UNIT_TEST(env_init, test_env_init_mm_gp10b_fusa, (void *)0, 0),
+	UNIT_TEST(mm_init_bar2_vm_s0, test_gp10b_mm_init_bar2_vm, (void *)F_INIT_BAR2_VM_DEFAULT, 0),
+	UNIT_TEST(mm_init_bar2_vm_s1, test_gp10b_mm_init_bar2_vm, (void *)F_INIT_BAR2_VM_INIT_VM_FAIL, 0),
+	UNIT_TEST(mm_init_bar2_vm_s2, test_gp10b_mm_init_bar2_vm, (void *)F_INIT_BAR2_VM_ALLOC_INST_BLOCK_FAIL, 0),
+	UNIT_TEST(env_clean, test_env_clean_mm_gp10b_fusa, NULL, 0),
+};
+
+UNIT_MODULE(mm_gp10b_fusa, mm_gp10b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_GP10B_FUSA_H
+#define UNIT_MM_HAL_GP10B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-gp10b_fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.gp10b_fusa
+ */
+
+/**
+ * Test specification for: test_env_init_mm_gp10b_fusa
+ *
+ * Description: Initialize environment for MM tests
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Init HALs and initialize VMs similar to nvgpu_init_system_vm().
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_init_mm_gp10b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_gp10b_mm_init_bar2_vm
+ *
+ * Description: Initialize bar2 VM
+ *
+ * Test Type: Feature, Error injection
+ *
+ * Targets: gops_mm.init_bar2_vm, gp10b_mm_init_bar2_vm, gops_mm.remove_bar2_vm,
+ * gp10b_mm_remove_bar2_vm
+ *
+ * Input: test_env_init, args (value can be F_INIT_BAR2_VM_DEFAULT,
+ *        F_INIT_BAR2_VM_INIT_VM_FAIL or F_INIT_BAR2_VM_ALLOC_INST_BLOCK_FAIL)
+ *
+ * Steps:
+ * - Allocate and initialize bar2 VM.
+ * - Check failure cases when allocation fails.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gp10b_mm_init_bar2_vm(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/**
+ * Test specification for: test_env_clean_mm_gp10b_fusa
+ *
+ * Description: Cleanup test environment
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Destroy memory and VMs initialized for the test.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_clean_mm_gp10b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_GP10B_FUSA_H */

userspace/units/mm/hal/gv11b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = mm-gv11b-fusa.o
+MODULE = mm-gv11b-fusa
+
+include ../../../Makefile.units

userspace/units/mm/hal/gv11b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=mm-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gv11b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=mm-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.c

@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/vm.h>
+
+#include "os/posix/os_posix.h"
+
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+#include "hal/mc/mc_gp10b.h"
+
+#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
+
+#include "mm-gv11b-fusa.h"
+
+/*
+ * Write callback (for all nvgpu_writel calls).
+ */
+static void writel_access_reg_fn(struct gk20a *g,
+			     struct nvgpu_reg_access *access)
+{
+	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+}
+
+/*
+ * Read callback, similar to the write callback above.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+			    struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+/*
+ * Define all the callbacks to be used during the test. Typically all
+ * write operations use the same callback, likewise for all read operations.
+ */
+static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+};
+
+static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
+{
+	if (is_iGPU) {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	} else {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
+	}
+}
+
+static int init_mm(struct unit_module *m, struct gk20a *g)
+{
+	u64 low_hole, aperture_size;
+	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
+	struct mm_gk20a *mm = &g->mm;
+	int err;
+
+	p->mm_is_iommuable = true;
+
+	/* Minimum HALs for page_table */
+	memset(&g->ops.bus, 0, sizeof(g->ops.bus));
+	memset(&g->ops.fb, 0, sizeof(g->ops.fb));
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.ramin.init_pdb = gv11b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+	g->ops.mc.intr_stall_unit_config = mc_gp10b_intr_stall_unit_config;
+	g->ops.mm.gmmu.get_default_big_page_size =
+					nvgpu_gmmu_default_big_page_size;
+	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
+	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
+	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
+	g->ops.mm.mmu_fault.info_mem_destroy =
+					gv11b_mm_mmu_fault_info_mem_destroy;
+
+	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
+
+	/* Register space: FB_MMU */
+	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
+		unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
+	}
+
+	/*
+	 * Initialize VM space for system memory to be used throughout this
+	 * unit module.
+	 * Values below are similar to those used in nvgpu_init_system_vm()
+	 */
+	low_hole = SZ_4K * 16UL;
+	aperture_size = GK20A_PMU_VA_SIZE;
+	mm->pmu.aperture_size = GK20A_PMU_VA_SIZE;
+
+	mm->pmu.vm = nvgpu_vm_init(g,
+				   g->ops.mm.gmmu.get_default_big_page_size(),
+				   low_hole,
+				   0ULL,
+				   nvgpu_safe_sub_u64(aperture_size, low_hole),
+				   0ULL,
+				   true,
+				   false,
+				   false,
+				   "system");
+	if (mm->pmu.vm == NULL) {
+		unit_return_fail(m, "'system' nvgpu_vm_init failed\n");
+	}
+
+	/* BAR2 memory space */
+	mm->bar2.aperture_size = U32(32) << 20U;
+	mm->bar2.vm = nvgpu_vm_init(g,
+		g->ops.mm.gmmu.get_default_big_page_size(),
+		SZ_4K, 0ULL, nvgpu_safe_sub_u64(mm->bar2.aperture_size, SZ_4K),
+		0ULL, false, false, false, "bar2");
+	if (mm->bar2.vm == NULL) {
+		unit_return_fail(m, "'bar2' nvgpu_vm_init failed\n");
+	}
+
+	/*
+	 * This initialization will make sure that correct aperture mask
+	 * is returned */
+	g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM;
+	g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
+
+	/* Init MM H/W */
+	err = g->ops.mm.setup_hw(g);
+	if (err != 0) {
+		unit_return_fail(m, "init_mm_setup_hw failed code=%d\n", err);
+	}
+
+	return UNIT_SUCCESS;
+}
+
+int test_env_init_mm_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+
+	init_platform(m, g, true);
+
+	if (init_mm(m, g) != 0) {
+		unit_return_fail(m, "nvgpu_init_mm_support failed\n");
+	}
+
+	return UNIT_SUCCESS;
+}
+
+#define F_INIT_INST_BLOCK_SET_BIG_PAGE_ZERO		1ULL
+#define F_INIT_INST_BLOCK_SET_BIG_PAGE_SIZE_NULL	2ULL
+#define F_INIT_INST_BLOCK_INIT_SUBCTX_PDB_NULL		3ULL
+
+int test_gv11b_mm_init_inst_block(struct unit_module *m, struct gk20a *g,
+					void *args)
+{
+	struct nvgpu_mem inst_block;
+	struct gpu_ops gops = g->ops;
+	int err;
+	u64 branch = (u64)args;
+	u32 big_page_size;
+
+	big_page_size = branch == F_INIT_INST_BLOCK_SET_BIG_PAGE_ZERO ?
+			0U : g->ops.mm.gmmu.get_default_big_page_size();
+
+	g->ops.ramin.set_big_page_size =
+		branch == F_INIT_INST_BLOCK_SET_BIG_PAGE_SIZE_NULL ?
+		NULL : gops.ramin.set_big_page_size;
+
+	g->ops.ramin.init_subctx_pdb =
+		branch == F_INIT_INST_BLOCK_INIT_SUBCTX_PDB_NULL ?
+		NULL : gops.ramin.init_subctx_pdb;
+
+	err = nvgpu_alloc_inst_block(g, &inst_block);
+	if (err != 0) {
+		unit_return_fail(m, "could not alloc inst block\n");
+	}
+
+	gv11b_mm_init_inst_block(&inst_block, g->mm.bar2.vm, big_page_size);
+
+	return UNIT_SUCCESS;
+}
+
+int test_gv11b_mm_is_bar1_supported(struct unit_module *m, struct gk20a *g,
+					void *args)
+{
+	bool ret = gv11b_mm_is_bar1_supported(g);
+	if (ret != false) {
+		unit_return_fail(m, "FAIL! bar1 is supported on Volta\n");
+	}
+
+	return UNIT_SUCCESS;
+}
+
+int test_env_clean_mm_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	g->log_mask = 0;
+	g->ops.mm.mmu_fault.info_mem_destroy(g);
+	nvgpu_vm_put(g->mm.pmu.vm);
+	nvgpu_vm_put(g->mm.bar2.vm);
+
+	return UNIT_SUCCESS;
+}
+
+struct unit_module_test mm_gv11b_fusa_tests[] = {
+	UNIT_TEST(env_init, test_env_init_mm_gv11b_fusa, (void *)0, 0),
+	UNIT_TEST(inst_block_s0, test_gv11b_mm_init_inst_block, (void *)0U, 0),
+	UNIT_TEST(inst_block_s1, test_gv11b_mm_init_inst_block, (void *)1U, 0),
+	UNIT_TEST(inst_block_s2, test_gv11b_mm_init_inst_block, (void *)2U, 0),
+	UNIT_TEST(inst_block_s3, test_gv11b_mm_init_inst_block, (void *)3U, 0),
+	UNIT_TEST(is_bar1_supported, test_gv11b_mm_is_bar1_supported, NULL, 0),
+	UNIT_TEST(env_clean, test_env_clean_mm_gv11b_fusa, NULL, 0),
+};
+
+UNIT_MODULE(mm_gv11b_fusa, mm_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.h

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_GV11B_FUSA_H
+#define UNIT_MM_HAL_GV11B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-gv11b-fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.gv11b_fusa
+ */
+
+/**
+ * Test specification for: test_env_init_mm_gv11b_fusa
+ *
+ * Description: Initialize environment for MM tests
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Init HALs and initialize VMs similar to nvgpu_init_system_vm().
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_init_mm_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_init_inst_block
+ *
+ * Description: Initialize instance block
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.init_inst_block, gv11b_mm_init_inst_block
+ *
+ * Input: test_env_init, args (value can be F_INIT_INST_BLOCK_SET_BIG_PAGE_ZERO,
+ *        F_INIT_INST_BLOCK_SET_BIG_PAGE_SIZE_NULL or
+ *        F_INIT_INST_BLOCK_INIT_SUBCTX_PDB_NULL)
+ *
+ * Steps:
+ * - Allocate memory for instance block.
+ * - Initialize GPU accessible instance block memory.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_init_inst_block(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_is_bar1_supported
+ *
+ * Description: Test if bar1_is_supported
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.is_bar1_supported, gv11b_mm_is_bar1_supported
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Execute gv11b_mm_is_bar1_supported() to check if bar1 is supported.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_is_bar1_supported(struct unit_module *m, struct gk20a *g,
+					void *args);
+/**
+ * Test specification for: test_env_clean_mm_gv11b_fusa
+ *
+ * Description: Cleanup test environment
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Destroy memory and VMs initialized for the test.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_clean_mm_gv11b_fusa(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_GV11B_FUSA_H */

userspace/units/mm/hal/mmu_fault/gv11b_fusa/Makefile

@@ -0,0 +1,26 @@
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = mmu-fault-gv11b-fusa.o
+MODULE = mmu-fault-gv11b-fusa
+
+include ../../../../Makefile.units

userspace/units/mm/hal/mmu_fault/gv11b_fusa/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=mmu-fault-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/mmu_fault/gv11b_fusa/Makefile.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=mmu-fault-gv11b-fusa
+
+include $(NV_COMPONENT_DIR)/../../../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c

@@ -0,0 +1,853 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include <stdlib.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include <unit/io.h>
+#include <unit/unit.h>
+
+#include <nvgpu/io.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/posix/io.h>
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/types.h>
+#include <nvgpu/fifo.h>
+#include <nvgpu/vm.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/engines.h>
+#include <nvgpu/preempt.h>
+#include <nvgpu/cic.h>
+#include <nvgpu/nvgpu_init.h>
+#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
+#include <nvgpu/posix/dma.h>
+#include <nvgpu/posix/posix-fault-injection.h>
+
+#include "os/posix/os_posix.h"
+
+#include "hal/init/hal_gv11b.h"
+#include "hal/fb/fb_gm20b.h"
+#include "hal/fb/fb_gv11b.h"
+#include "hal/fb/fb_mmu_fault_gv11b.h"
+#include "hal/fb/intr/fb_intr_gv11b.h"
+#include "hal/fifo/channel_gk20a.h"
+#include "hal/fifo/channel_gv11b.h"
+#include "hal/fifo/preempt_gv11b.h"
+#include "hal/fifo/ramin_gk20a.h"
+#include "hal/fifo/ramin_gv11b.h"
+#include "hal/mm/cache/flush_gk20a.h"
+#include "hal/mm/gmmu/gmmu_gp10b.h"
+#include "hal/mm/gmmu/gmmu_gv11b.h"
+#include "hal/mm/mm_gp10b.h"
+#include "hal/mm/mm_gv11b.h"
+#include "hal/cic/cic_gv11b.h"
+
+#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
+#include "mmu-fault-gv11b-fusa.h"
+
+static u32 global_count;
+static u32 count;
+
+/*
+ * Write callback (for all nvgpu_writel calls).
+ */
+static void writel_access_reg_fn(struct gk20a *g,
+			     struct nvgpu_reg_access *access)
+{
+		nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+}
+
+/*
+ * Read callback, similar to the write callback above.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+			    struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+/*
+ * Define all the callbacks to be used during the test. Typically all
+ * write operations use the same callback, likewise for all read operations.
+ */
+static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+};
+
+static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
+{
+	if (is_iGPU) {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
+	} else {
+		nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
+	}
+}
+
+static u32 stub_channel_count(struct gk20a *g)
+{
+	return 32;
+}
+
+static int stub_mm_l2_flush(struct gk20a *g, bool invalidate)
+{
+	return 0;
+}
+
+static int init_mm(struct unit_module *m, struct gk20a *g)
+{
+	u64 low_hole, aperture_size;
+	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
+	struct mm_gk20a *mm = &g->mm;
+	int err;
+
+	p->mm_is_iommuable = true;
+
+	/* Minimum HALs for page_table */
+	g->ops.mm.gmmu.get_default_big_page_size =
+					nvgpu_gmmu_default_big_page_size;
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
+	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
+	g->ops.ramin.init_pdb = gv11b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
+	g->ops.channel.count = stub_channel_count;
+	g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
+	g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
+	g->ops.mm.gmmu.get_iommu_bit = gp10b_mm_get_iommu_bit;
+	g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;
+	g->ops.mm.cache.l2_flush = stub_mm_l2_flush;
+	g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
+	g->ops.mm.gmmu.get_max_page_table_levels =
+						gp10b_get_max_page_table_levels;
+	g->ops.mm.mmu_fault.info_mem_destroy =
+					gv11b_mm_mmu_fault_info_mem_destroy;
+	g->ops.mm.mmu_fault.parse_mmu_fault_info =
+					gv11b_mm_mmu_fault_parse_mmu_fault_info;
+
+	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
+
+	/* Register space: FB_MMU */
+	if (nvgpu_posix_io_add_reg_space(g, fb_mmu_ctrl_r(), 0x800) != 0) {
+		unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
+	}
+
+	/*
+	 * Initialize VM space for system memory to be used throughout this
+	 * unit module.
+	 * Values below are similar to those used in nvgpu_init_system_vm()
+	 */
+	low_hole = SZ_4K * 16UL;
+	aperture_size = GK20A_PMU_VA_SIZE;
+	mm->pmu.aperture_size = GK20A_PMU_VA_SIZE;
+
+	mm->pmu.vm = nvgpu_vm_init(g,
+				   g->ops.mm.gmmu.get_default_big_page_size(),
+				   low_hole,
+				   0ULL,
+				   nvgpu_safe_sub_u64(aperture_size, low_hole),
+				   0ULL,
+				   true,
+				   false,
+				   false,
+				   "system");
+	if (mm->pmu.vm == NULL) {
+		unit_return_fail(m, "'system' nvgpu_vm_init failed\n");
+	}
+
+	/* BAR2 memory space */
+	mm->bar2.aperture_size = U32(32) << 20U;
+	mm->bar2.vm = nvgpu_vm_init(g,
+		g->ops.mm.gmmu.get_default_big_page_size(),
+		SZ_4K, 0ULL, nvgpu_safe_sub_u64(mm->bar2.aperture_size, SZ_4K),
+		0ULL, false, false, false, "bar2");
+	if (mm->bar2.vm == NULL) {
+		unit_return_fail(m, "'bar2' nvgpu_vm_init failed\n");
+	}
+
+	err = nvgpu_pd_cache_init(g);
+	if (err != 0) {
+		unit_return_fail(m, "PD cache init failed\n");
+	}
+
+	/*
+	 * This initialization will make sure that correct aperture mask
+	 * is returned */
+	g->mm.mmu_wr_mem.aperture = APERTURE_SYSMEM;
+	g->mm.mmu_rd_mem.aperture = APERTURE_SYSMEM;
+
+	return UNIT_SUCCESS;
+}
+
+int test_env_init_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	g->log_mask = 0;
+
+	init_platform(m, g, true);
+
+	if (init_mm(m, g) != 0) {
+		unit_return_fail(m, "nvgpu_init_mm_support failed\n");
+	}
+
+	g->ops.cic.init = gv11b_cic_init;
+	g->ops.cic.report_err = nvgpu_cic_report_err_safety_services;
+
+	if (nvgpu_cic_init_common(g) != 0) {
+		unit_return_fail(m, "Failed to initialize CIC\n");
+	}
+
+	return UNIT_SUCCESS;
+}
+
+#define F_MMU_FAULT_SETUP_SW_FAULT_BUF_ALLOC_FAIL	0
+#define F_MMU_FAULT_SETUP_SW_DEFAULT			1
+
+static const char *f_mmu_fault_setup_sw[] = {
+	"mmu_fault_setup_sw_alloc_fail",
+	"mmu_fault_setup_sw_default",
+};
+
+int test_gv11b_mm_mmu_fault_setup_sw(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	struct nvgpu_posix_fault_inj *l_dma_fi;
+	u64 branch = (u64)args;
+
+	l_dma_fi = nvgpu_dma_alloc_get_fault_injection();
+
+	nvgpu_posix_enable_fault_injection(l_dma_fi,
+		branch == F_MMU_FAULT_SETUP_SW_FAULT_BUF_ALLOC_FAIL ?
+			true : false, 0);
+
+	err = gv11b_mm_mmu_fault_setup_sw(g);
+	unit_assert(err == 0, goto done);
+
+	if (branch == F_MMU_FAULT_SETUP_SW_FAULT_BUF_ALLOC_FAIL) {
+		unit_assert(
+		g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].aperture
+						== APERTURE_INVALID, goto done);
+	} else {
+		unit_assert(
+		g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].aperture
+						== APERTURE_SYSMEM, goto done);
+		unit_assert(
+		g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].gpu_va
+						!= 0ULL, goto done);
+	}
+	gv11b_mm_mmu_fault_info_mem_destroy(g);
+
+	unit_assert(g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].aperture
+						== APERTURE_INVALID, goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_mmu_fault_setup_sw[branch]);
+	}
+	nvgpu_posix_enable_fault_injection(l_dma_fi, false, 0);
+	return ret;
+}
+
+static void stub_fb_fault_buf_configure_hw(struct gk20a *g, u32 index)
+{
+	count = global_count;
+}
+
+int test_gv11b_mm_mmu_fault_setup_hw(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	enum nvgpu_aperture fb_aperture_orig = APERTURE_INVALID;
+
+	global_count = 0U;
+	count = 1U;
+
+	g->ops.fb.fault_buf_configure_hw = stub_fb_fault_buf_configure_hw;
+
+	err = gv11b_mm_mmu_fault_setup_sw(g);
+	unit_assert(err == 0, goto done);
+
+	gv11b_mm_mmu_fault_setup_hw(g);
+	unit_assert(count == global_count, goto done);
+	global_count++;
+
+	fb_aperture_orig =
+		g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].aperture;
+	g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].aperture =
+		APERTURE_INVALID;
+
+	gv11b_mm_mmu_fault_setup_hw(g);
+	unit_assert(count != global_count, goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s failed\n", __func__);
+	}
+	g->mm.hw_fault_buf[NVGPU_MMU_FAULT_NONREPLAY_INDX].aperture =
+		fb_aperture_orig;
+	gv11b_mm_mmu_fault_info_mem_destroy(g);
+	return ret;
+}
+
+#define F_MMU_FAULT_DISABLE_HW_FALSE	0
+#define F_MMU_FAULT_DISABLE_HW_TRUE	1
+
+static const char *f_mmu_fault_disable[] = {
+	"mmu_fault_disable_hw_false",
+	"mmu_fault_disable_hw_true",
+};
+
+static bool fault_buf_enabled;
+
+static bool stub_fb_is_fault_buf_enabled(struct gk20a *g, u32 index)
+{
+	count = global_count;
+	return fault_buf_enabled;
+}
+
+static void stub_fb_fault_buf_set_state_hw(struct gk20a *g, u32 index, u32 state)
+{
+	global_count += 2U;
+}
+
+int test_gv11b_mm_mmu_fault_disable_hw(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	int err = 0U;
+	u64 branch = (u64)args;
+	struct gpu_ops gops = g->ops;
+
+	global_count = 10U;
+	count = 0U;
+
+	err = gv11b_mm_mmu_fault_setup_sw(g);
+	unit_assert(err == 0, goto done);
+
+	g->ops.fb.is_fault_buf_enabled = stub_fb_is_fault_buf_enabled;
+	g->ops.fb.fault_buf_set_state_hw = stub_fb_fault_buf_set_state_hw;
+	fault_buf_enabled = branch == F_MMU_FAULT_DISABLE_HW_FALSE ?
+				false : true;
+
+	gv11b_mm_mmu_fault_disable_hw(g);
+	unit_assert(count == 10U, goto done);
+	unit_assert(global_count == (10U + (2U * fault_buf_enabled)), goto done);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_mmu_fault_disable[branch]);
+	}
+	gv11b_mm_mmu_fault_info_mem_destroy(g);
+	g->ops = gops;
+	return ret;
+}
+
+#define F_MMU_FAULT_ENG_ID_INVALID	0
+#define F_MMU_FAULT_ENG_ID_BAR2		1
+#define F_MMU_FAULT_ENG_ID_PHYSICAL	2
+
+static const char *f_mmu_fault_notify[] = {
+	"mmu_fault_notify_eng_id_invalid",
+	"mmu_fault_notify_eng_id_bar2",
+	"mmu_fault_notify_eng_id_physical",
+};
+
+static void stub_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g)
+{
+}
+
+static int stub_bus_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst)
+{
+	return 0;
+}
+
+static u32 stub_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id)
+{
+	return INVAL_ID;
+}
+
+int test_gv11b_mm_mmu_fault_handle_other_fault_notify(struct unit_module *m,
+					struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+	int err;
+	struct gpu_ops gops = g->ops;
+	u32 reg_val;
+
+	g->ops.fb.read_mmu_fault_inst_lo_hi =
+					gv11b_fb_read_mmu_fault_inst_lo_hi;
+	g->ops.fb.read_mmu_fault_addr_lo_hi =
+					gv11b_fb_read_mmu_fault_addr_lo_hi;
+	g->ops.fb.read_mmu_fault_info = gv11b_fb_read_mmu_fault_info;
+	g->ops.fb.write_mmu_fault_status = gv11b_fb_write_mmu_fault_status;
+	g->ops.ce.mthd_buffer_fault_in_bar2_fault =
+					stub_ce_mthd_buffer_fault_in_bar2_fault;
+	g->ops.bus.bar2_bind = stub_bus_bar2_bind;
+	g->ops.fifo.mmu_fault_id_to_pbdma_id =
+					stub_fifo_mmu_fault_id_to_pbdma_id;
+
+	reg_val = branch == F_MMU_FAULT_ENG_ID_BAR2 ?
+			gmmu_fault_mmu_eng_id_bar2_v() :
+			branch == F_MMU_FAULT_ENG_ID_PHYSICAL ?
+				gmmu_fault_mmu_eng_id_physical_v() : 0U;
+	nvgpu_writel(g, fb_mmu_fault_inst_lo_r(), reg_val);
+
+	err = gv11b_mm_mmu_fault_setup_sw(g);
+	unit_assert(err == 0, goto done);
+
+	gv11b_mm_mmu_fault_handle_other_fault_notify(g,
+					fb_mmu_fault_status_valid_set_f());
+
+	if (branch == F_MMU_FAULT_ENG_ID_BAR2) {
+		unit_assert(g->mm.fault_info[
+			NVGPU_MMU_FAULT_NONREPLAY_INDX].mmu_engine_id ==
+			gmmu_fault_mmu_eng_id_bar2_v(), goto done);
+	} else if (branch == F_MMU_FAULT_ENG_ID_PHYSICAL) {
+		unit_assert(g->mm.fault_info[
+			NVGPU_MMU_FAULT_NONREPLAY_INDX].mmu_engine_id ==
+			gmmu_fault_mmu_eng_id_physical_v(), goto done);
+	} else {
+		unit_assert(g->mm.fault_info[
+			NVGPU_MMU_FAULT_NONREPLAY_INDX].mmu_engine_id ==
+			0U, goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_mmu_fault_notify[branch]);
+	}
+	gv11b_mm_mmu_fault_info_mem_destroy(g);
+	g->ops = gops;
+	return ret;
+}
+
+#define F_MMU_FAULT_INFO_FAULT_TYPE_INVALID		0x01ULL
+#define F_MMU_FAULT_INFO_CLIENT_TYPE_INVALID		0x02ULL
+#define F_MMU_FAULT_INFO_CLIENT_TYPE_HUB		0x04ULL
+#define F_MMU_FAULT_INFO_CLIENT_TYPE_GPC		0x08ULL
+#define F_MMU_FAULT_INFO_CLIENT_ID_INVALID		0x10ULL
+
+#define F_MMU_FAULT_PARSE_DEFAULT			0x00ULL
+/* F_MMU_FAULT_INFO_FAULT_TYPE_INVALID */
+#define F_MMU_FAULT_PARSE_FAULT_TYPE_INVALID		0x01ULL
+/* F_MMU_FAULT_INFO_CLIENT_TYPE_INVALID */
+#define F_MMU_FAULT_PARSE_CLIENT_TYPE_INVALID		0x02ULL
+/* F_MMU_FAULT_INFO_CLIENT_TYPE_HUB */
+#define F_MMU_FAULT_PARSE_CLIENT_TYPE_HUB		0x04ULL
+/* F_MMU_FAULT_INFO_CLIENT_TYPE_HUB + F_MMU_FAULT_INFO_CLIENT_ID_INVALID */
+#define F_MMU_FAULT_PARSE_CLIENT_HUB_ID_INVALID		0x14ULL
+/* F_MMU_FAULT_INFO_CLIENT_TYPE_GPC */
+#define F_MMU_FAULT_PARSE_CLIENT_TYPE_GPC		0x08ULL
+/* F_MMU_FAULT_INFO_CLIENT_TYPE_GPC + F_MMU_FAULT_INFO_CLIENT_ID_INVALID */
+#define F_MMU_FAULT_PARSE_CLIENT_GPC_ID_INVALID		0x18ULL
+
+
+int test_gv11b_mm_mmu_fault_parse_mmu_fault_info(struct unit_module *m,
+					struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+	struct mmu_fault_info *mmufault =
+			&g->mm.fault_info[NVGPU_MMU_FAULT_NONREPLAY_INDX];
+
+	mmufault->fault_type = branch & F_MMU_FAULT_INFO_FAULT_TYPE_INVALID ?
+				1000U : 0U;
+	mmufault->client_type = branch & F_MMU_FAULT_INFO_CLIENT_TYPE_INVALID ?
+		1000U :
+		branch & F_MMU_FAULT_INFO_CLIENT_TYPE_HUB ?
+			gmmu_fault_client_type_hub_v() :
+			branch & F_MMU_FAULT_INFO_CLIENT_TYPE_GPC ?
+				gmmu_fault_client_type_gpc_v() : 0U;
+
+	mmufault->client_id = branch & F_MMU_FAULT_INFO_CLIENT_ID_INVALID ?
+				1000U : 0U;
+
+	EXPECT_BUG(gv11b_mm_mmu_fault_parse_mmu_fault_info(mmufault));
+
+	if (!(branch & F_MMU_FAULT_PARSE_FAULT_TYPE_INVALID)) {
+		unit_assert(strcmp(mmufault->fault_type_desc, "invalid pde") == 0, goto done);
+	}
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: failed\n", __func__);
+	}
+	return ret;
+}
+
+static u32 ret_num_lce;
+
+static u32 stub_top_get_num_lce(struct gk20a *g)
+{
+	return ret_num_lce;
+}
+
+static int stub_runlist_update(struct gk20a *g,
+			       struct nvgpu_runlist *rl,
+			       struct nvgpu_channel *ch,
+			       bool add, bool wait_for_finish)
+{
+	return 0;
+}
+
+static void stub_set_err_notifier_if_empty(struct nvgpu_channel *ch, u32 error)
+{
+}
+
+static u32 stub_gr_init_get_no_of_sm(struct gk20a *g)
+{
+	return 8;
+}
+
+#define F_MMU_FAULT_VALID			0x01ULL
+#define F_NVGPU_POWERED_ON			0x02ULL
+#define F_MMU_FAULT_ENG_ID_CE0			0x04ULL
+#define F_NUM_LCE_0				0x08ULL
+#define F_MMU_FAULT_NON_REPLAYABLE		0x10ULL
+#define F_MMU_FAULT_TYPE_INST_BLOCK		0x20ULL
+#define F_MMU_FAULT_REFCH			0x40ULL
+#define F_FAULTED_ENGINE_INVALID		0x80ULL
+#define F_MMU_NACK_HANDLED			0x100ULL
+#define F_TSG_VALID				0x200ULL
+
+/* !F_MMU_FAULT_VALID */
+#define F_MMU_HANDLER_FAULT_INVALID			0x00ULL
+/* F_MMU_FAULT_VALID + !F_NVGPU_POWERED_ON */
+#define F_MMU_HANDLER_NVGPU_POWERED_OFF			0x01ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_ENG_ID_CE0 */
+#define F_MMU_HANDLER_CE_DEFAULT			0x07ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_ENG_ID_CE0 +
+	F_NUM_LCE_0 */
+#define F_MMU_HANDLER_CE_LCE_0				0x0FULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_ENG_ID_CE0 +
+	F_MMU_FAULT_REFCH */
+#define F_MMU_HANDLER_CE_REFCH				0x47ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_NON_REPLAYABLE */
+#define F_MMU_HANDLER_NON_REPLAYABLE_DEFAULT		0x13ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_NON_REPLAYABLE +
+ F_MMU_FAULT_TYPE_INST_BLOCK */
+#define F_MMU_HANDLER_NON_REPLAYABLE_INST_BLOCK		0x33ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_NON_REPLAYABLE +
+	F_MMU_FAULT_REFCH */
+#define F_MMU_HANDLER_NON_REPLAYABLE_REFCH		0x53ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_NON_REPLAYABLE +
+	F_MMU_FAULT_REFCH + F_MMU_NACK_HANDLED*/
+#define F_MMU_HANDLER_NON_REPLAYABLE_REFCH_NACK_HNDLD	0x153ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_NON_REPLAYABLE +
+	F_FAULTED_ENGINE_INVALID */
+#define F_MMU_HANDLER_NON_REPLAYABLE_FAULTED_INVALID	0x93ULL
+/* F_MMU_FAULT_VALID + F_NVGPU_POWERED_ON + F_MMU_FAULT_NON_REPLAYABLE +
+	F_NUM_LCE_0 + F_TSG_VALID */
+#define F_MMU_HANDLER_NON_REPLAYABLE_TSG		0x29BULL
+
+static const char *f_mmu_handler[] = {
+	[F_MMU_HANDLER_FAULT_INVALID] = "mmu_handler_fault_invalid",
+	[F_MMU_HANDLER_NVGPU_POWERED_OFF] = "mmu_handler_nvgpu_powered_off",
+	[F_MMU_HANDLER_CE_DEFAULT] = "mmu_handler_ce_default",
+	[F_MMU_HANDLER_CE_LCE_0] = "mmu_handler_ce_with_lce_0",
+	[F_MMU_HANDLER_CE_REFCH] = "mmu_handler_ce_refch_valid",
+	[F_MMU_HANDLER_NON_REPLAYABLE_DEFAULT] =
+				"mmu_handler_non-replayable_default",
+	[F_MMU_HANDLER_NON_REPLAYABLE_INST_BLOCK] =
+				"mmu_handler_non-replayable_inst_block",
+	[F_MMU_HANDLER_NON_REPLAYABLE_REFCH] =
+				"mmu_handler_non-replayable_refch_valid",
+	[F_MMU_HANDLER_NON_REPLAYABLE_REFCH_NACK_HNDLD] =
+				"mmu_handler_non-replayable_refch_nack_handled",
+	[F_MMU_HANDLER_NON_REPLAYABLE_FAULTED_INVALID] =
+			"mmu_handler_non-replayable_faulted_engine_invalid",
+	[F_MMU_HANDLER_NON_REPLAYABLE_TSG] =
+				"mmu_handler_non-replayable_tsg_valid",
+};
+
+int test_handle_mmu_fault_common(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	int ret = UNIT_FAIL;
+	u64 branch = (u64)args;
+	int err;
+	u32 invalidate_replay_val;
+	struct gpu_ops gops = g->ops;
+	struct nvgpu_channel chA = {0};
+	struct nvgpu_channel *chB = NULL;
+	struct nvgpu_tsg *tsg = NULL;
+	struct mmu_fault_info *mmufault =
+			&g->mm.fault_info[NVGPU_MMU_FAULT_NONREPLAY_INDX];
+
+	g->ops.top.get_num_lce = stub_top_get_num_lce;
+	g->sw_quiesce_pending = true;
+
+	err = gv11b_mm_mmu_fault_setup_sw(g);
+	unit_assert(err == 0, goto done);
+
+	mmufault->valid = branch & F_MMU_FAULT_VALID ? true : false;
+	nvgpu_set_power_state(g, branch & F_NVGPU_POWERED_ON ?
+			NVGPU_STATE_POWERED_ON : NVGPU_STATE_POWERED_OFF);
+	mmufault->mmu_engine_id = branch & F_MMU_FAULT_ENG_ID_CE0 ?
+				gmmu_fault_mmu_eng_id_ce0_v() :
+				gmmu_fault_mmu_eng_id_ce0_v() - 1U;
+	ret_num_lce = branch & F_NUM_LCE_0 ? 0U : 5U;
+	mmufault->replayable_fault = branch & F_MMU_FAULT_NON_REPLAYABLE ?
+					false : true;
+	mmufault->fault_type = branch & F_MMU_FAULT_TYPE_INST_BLOCK ?
+			gmmu_fault_type_unbound_inst_block_v() : 0U;
+	mmufault->faulted_engine = branch & F_FAULTED_ENGINE_INVALID ?
+						NVGPU_INVALID_ENG_ID : 0U;
+
+	if (branch & F_MMU_FAULT_REFCH) {
+		/* Init chA */
+		chA.g = g;
+		chA.tsgid = NVGPU_INVALID_TSG_ID;
+		nvgpu_atomic_set(&chA.ref_count, 2);
+		chA.mmu_nack_handled = branch & F_MMU_NACK_HANDLED ?
+								true : false;
+		mmufault->refch = &chA;
+	} else if (branch & F_TSG_VALID) {
+		/* Init TSG and chB */
+		g->ops.gr.init.get_no_of_sm = stub_gr_init_get_no_of_sm;
+		g->ops.runlist.update =	stub_runlist_update;
+		g->ops.tsg.default_timeslice_us =
+						nvgpu_tsg_default_timeslice_us;
+		g->ops.channel.alloc_inst = nvgpu_channel_alloc_inst;
+		g->ops.channel.set_error_notifier =
+						stub_set_err_notifier_if_empty;
+		g->ops.channel.disable = gk20a_channel_disable;
+		g->ops.channel.unbind = gv11b_channel_unbind;
+		g->ops.channel.free_inst = nvgpu_channel_free_inst;
+		g->ops.tsg.disable = nvgpu_tsg_disable;
+		g->ops.fifo.preempt_tsg = nvgpu_fifo_preempt_tsg;
+		g->aggressive_sync_destroy_thresh = 0U;
+
+		g->fifo.g = g;
+
+		err = nvgpu_channel_setup_sw(g);
+		unit_assert(err == 0, goto done);
+
+		err = nvgpu_tsg_setup_sw(g);
+		unit_assert(err == 0, goto done);
+
+		tsg = nvgpu_tsg_open(g, getpid());
+		unit_assert(tsg != NULL, goto done);
+
+		chB = nvgpu_channel_open_new(g, U32_MAX, false,
+							getpid(), getpid());
+		unit_assert(chB != NULL, goto done);
+
+		err = nvgpu_tsg_bind_channel(tsg, chB);
+		unit_assert(err == 0, goto done);
+
+		mmufault->refch = chB;
+
+	} else {
+		mmufault->refch = NULL;
+	}
+
+	gv11b_mm_mmu_fault_handle_mmu_fault_common(g, mmufault,
+							&invalidate_replay_val);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__, f_mmu_handler[branch]);
+	}
+
+	nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF);
+	gv11b_mm_mmu_fault_info_mem_destroy(g);
+	if (chB != NULL) {
+		nvgpu_atomic_set(&chB->ref_count, 1);
+		nvgpu_channel_close(chB);
+	}
+	if (tsg != NULL) {
+		nvgpu_ref_put(&tsg->refcount, nvgpu_tsg_release);
+	}
+	g->ops = gops;
+	return ret;
+}
+
+#define F_BUF_EMPTY	0x01ULL
+#define F_VALID_ENTRY	0x02ULL
+#define F_VALID_CH	0x04ULL
+
+#define F_HANDLE_NON_RPLYBLE_BUF_EMPTY		0x01ULL
+#define F_HANDLE_NON_RPLYBLE_INVALID_BUF_ENTRY	0x00ULL
+#define F_HANDLE_NON_RPLYBLE_VALID_BUF_ENTRY	0x02ULL
+#define F_HANDLE_NON_RPLYBLE_VALID_BUF_CH	0x06ULL
+
+static const char *f_mmu_fault_nonreplay[] = {
+	[F_HANDLE_NON_RPLYBLE_BUF_EMPTY] = "fault_buf_empty",
+	[F_HANDLE_NON_RPLYBLE_INVALID_BUF_ENTRY] = "buf_entry_invalid",
+	[F_HANDLE_NON_RPLYBLE_VALID_BUF_ENTRY] = "buf_entry_valid",
+	[F_HANDLE_NON_RPLYBLE_VALID_BUF_CH] = "validbuf_entry_and_refch",
+};
+
+static u32 get_idx, put_idx;
+
+static u32 stub_fb_read_mmu_fault_buffer_get(struct gk20a *g, u32 index)
+{
+	return get_idx;
+}
+
+static u32 stub_fb_read_mmu_fault_buffer_put(struct gk20a *g, u32 index)
+{
+	return put_idx;
+}
+
+static u32 stub_fb_read_mmu_fault_buffer_size(struct gk20a *g, u32 index)
+{
+	return 32U;
+}
+
+static void stub_fb_write_mmu_fault_buffer_get(struct gk20a *g, u32 index,
+								u32 reg_val)
+{
+}
+
+int test_handle_nonreplay_replay_fault(struct unit_module *m, struct gk20a *g,
+								void *args)
+{
+	int ret = UNIT_FAIL;
+	int err;
+	u64 branch = (u64)args;
+	u32 *data;
+	struct nvgpu_channel ch = {0};
+	struct gpu_ops gops = g->ops;
+
+	g->ops.fb.read_mmu_fault_buffer_get =
+					stub_fb_read_mmu_fault_buffer_get;
+	g->ops.fb.read_mmu_fault_buffer_put =
+					stub_fb_read_mmu_fault_buffer_put;
+	g->ops.fb.read_mmu_fault_buffer_size =
+					stub_fb_read_mmu_fault_buffer_size;
+	g->ops.fb.write_mmu_fault_buffer_get =
+					stub_fb_write_mmu_fault_buffer_get;
+	g->ops.fifo.mmu_fault_id_to_pbdma_id =
+					stub_fifo_mmu_fault_id_to_pbdma_id;
+
+	err = gv11b_mm_mmu_fault_setup_sw(g);
+	unit_assert(err == 0, goto done);
+
+	get_idx = 0;
+	put_idx = (branch & F_BUF_EMPTY) ? get_idx : 1U;
+
+	data = g->mm.hw_fault_buf[0].cpu_va;
+
+	data[gmmu_fault_buf_entry_valid_w()] = branch & F_VALID_ENTRY ?
+				gmmu_fault_buf_entry_valid_m() : 0U;
+
+	if (branch & F_VALID_CH) {
+		g->fifo.channel = &ch;
+		g->fifo.num_channels = 1;
+		ch.referenceable = true;
+	}
+
+	gv11b_mm_mmu_fault_handle_nonreplay_replay_fault(g, 0U, 0U);
+
+	ret = UNIT_SUCCESS;
+
+done:
+	if (ret != UNIT_SUCCESS) {
+		unit_err(m, "%s: %s failed\n", __func__,
+						f_mmu_fault_nonreplay[branch]);
+	}
+	gv11b_mm_mmu_fault_info_mem_destroy(g);
+	g->ops = gops;
+	return ret;
+}
+
+int test_env_clean_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
+						struct gk20a *g, void *args)
+{
+	g->log_mask = 0;
+
+	nvgpu_vm_put(g->mm.pmu.vm);
+	nvgpu_vm_put(g->mm.bar2.vm);
+
+	return UNIT_SUCCESS;
+}
+
+struct unit_module_test mm_mmu_fault_gv11b_fusa_tests[] = {
+	UNIT_TEST(env_init, test_env_init_mm_mmu_fault_gv11b_fusa, NULL, 0),
+	UNIT_TEST(setup_sw_s0, test_gv11b_mm_mmu_fault_setup_sw, (void *)F_MMU_FAULT_SETUP_SW_FAULT_BUF_ALLOC_FAIL, 0),
+	UNIT_TEST(setup_sw_s1, test_gv11b_mm_mmu_fault_setup_sw, (void *)F_MMU_FAULT_SETUP_SW_DEFAULT, 0),
+	UNIT_TEST(setup_hw, test_gv11b_mm_mmu_fault_setup_hw, NULL, 0),
+	UNIT_TEST(disable_hw_s0, test_gv11b_mm_mmu_fault_disable_hw, (void *)F_MMU_FAULT_DISABLE_HW_FALSE, 0),
+	UNIT_TEST(disable_hw_s1, test_gv11b_mm_mmu_fault_disable_hw, (void *)F_MMU_FAULT_DISABLE_HW_TRUE, 0),
+	UNIT_TEST(fault_notify_s0, test_gv11b_mm_mmu_fault_handle_other_fault_notify, (void *)F_MMU_FAULT_ENG_ID_INVALID, 0),
+	UNIT_TEST(fault_notify_s1, test_gv11b_mm_mmu_fault_handle_other_fault_notify, (void *)F_MMU_FAULT_ENG_ID_BAR2, 0),
+	UNIT_TEST(fault_notify_s2, test_gv11b_mm_mmu_fault_handle_other_fault_notify, (void *)F_MMU_FAULT_ENG_ID_PHYSICAL, 0),
+	UNIT_TEST(parse_info_s0, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_DEFAULT, 0),
+	UNIT_TEST(parse_info_s1, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_FAULT_TYPE_INVALID, 0),
+	UNIT_TEST(parse_info_s2, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_CLIENT_TYPE_INVALID, 0),
+	UNIT_TEST(parse_info_s3, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_CLIENT_TYPE_HUB, 0),
+	UNIT_TEST(parse_info_s4, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_CLIENT_HUB_ID_INVALID, 0),
+	UNIT_TEST(parse_info_s5, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_CLIENT_TYPE_GPC, 0),
+	UNIT_TEST(parse_info_s6, test_gv11b_mm_mmu_fault_parse_mmu_fault_info, (void *)F_MMU_FAULT_PARSE_CLIENT_GPC_ID_INVALID, 0),
+	UNIT_TEST(handle_mmu_common_s0, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_FAULT_INVALID, 0),
+	UNIT_TEST(handle_mmu_common_s1, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NVGPU_POWERED_OFF, 0),
+	UNIT_TEST(handle_mmu_common_s2, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_CE_DEFAULT, 0),
+	UNIT_TEST(handle_mmu_common_s3, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_CE_LCE_0, 0),
+	UNIT_TEST(handle_mmu_common_s4, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_CE_REFCH, 0),
+	UNIT_TEST(handle_mmu_common_s5, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_DEFAULT, 0),
+	UNIT_TEST(handle_mmu_common_s6, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_INST_BLOCK, 0),
+	UNIT_TEST(handle_mmu_common_s7, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_REFCH, 0),
+	UNIT_TEST(handle_mmu_common_s8, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_REFCH_NACK_HNDLD, 0),
+	UNIT_TEST(handle_mmu_common_s9, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_FAULTED_INVALID, 0),
+	UNIT_TEST(handle_mmu_common_s10, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_TSG, 2),
+	UNIT_TEST(handle_nonreplay_s0, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_BUF_EMPTY, 0),
+	UNIT_TEST(handle_nonreplay_s1, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_INVALID_BUF_ENTRY, 0),
+	UNIT_TEST(handle_nonreplay_s2, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_VALID_BUF_ENTRY, 0),
+	UNIT_TEST(handle_nonreplay_s3, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_VALID_BUF_CH, 0),
+	UNIT_TEST(env_clean, test_env_clean_mm_mmu_fault_gv11b_fusa, NULL, 0),
+};
+
+UNIT_MODULE(mmu_fault_gv11b_fusa, mm_mmu_fault_gv11b_fusa_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.h

@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UNIT_MM_HAL_MMU_FAULT_GV11B_FUSA_H
+#define UNIT_MM_HAL_MMU_FAULT_GV11B_FUSA_H
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-mm-hal-mmu_fault-gv11b_fusa
+ *  @{
+ *
+ * Software Unit Test Specification for mm.hal.mmu_fault.mmu_fault_gv11b_fusa
+ */
+
+/**
+ * Test specification for: test_env_init_mm_mmu_fault_gv11b_fusa
+ *
+ * Description: Initialize environment for MM tests
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: None
+ *
+ * Steps:
+ * - Init HALs and initialize VMs similar to nvgpu_init_system_vm().
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_init_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
+					struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_mmu_fault_setup_sw
+ *
+ * Description: Test mmu fault setup sw function
+ *
+ * Test Type: Feature, Error injection
+ *
+ * Targets: gops_mm.gops_mm_mmu_fault.setup_sw, gv11b_mm_mmu_fault_setup_sw,
+ * gops_mm.gops_mm_mmu_fault.info_mem_destroy,
+ * gv11b_mm_mmu_fault_info_mem_destroy
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check that mmu hw fault buffer is allocated and mapped.
+ * - Check that gv11b_mm_mmu_fault_info_mem_destroy() deallocates fault buffer
+ *   memory.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_mmu_fault_setup_sw(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/**
+ * Test specification for:
+ *
+ * Description: Test mmu fault setup hw function
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_mmu_fault.setup_hw, gv11b_mm_mmu_fault_setup_hw
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check that gv11b_mm_mmu_fault_setup_hw() configures fault buffer. Here,
+ *   buffer addr is written to memory to be used by h/w for fault notification.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_mmu_fault_setup_hw(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_mmu_fault_disable_hw
+ *
+ * Description: Test mmu fault disable hw function
+ *
+ * Test Type: Feature
+ *
+ * Targets: gops_mm.gops_mm_mmu_fault.disable_hw, gv11b_mm_mmu_fault_disable_hw
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check that gv11b_mm_mmu_fault_disable_hw() sets disabled state if fault
+ *   buf is enabled.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_mmu_fault_disable_hw(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_mmu_fault_handle_other_fault_notify
+ *
+ * Description: Test other fault notify
+ *
+ * Test Type: Feature
+ *
+ * Targets: gv11b_mm_mmu_fault_handle_other_fault_notify
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check that BAR2 / physical faults are recognized and notified.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_mmu_fault_handle_other_fault_notify(struct unit_module *m,
+					struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gv11b_mm_mmu_fault_parse_mmu_fault_info
+ *
+ * Description: Test mmu fault parse function
+ *
+ * Test Type: Feature
+ *
+ * Targets: gv11b_mm_mmu_fault_parse_mmu_fault_info
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Parse mmu fault info such as fault type, client type and client id.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_gv11b_mm_mmu_fault_parse_mmu_fault_info(struct unit_module *m,
+					struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_handle_mmu_fault_common
+ *
+ * Description: Test mmu fault handler
+ *
+ * Test Type: Feature
+ *
+ * Targets: gv11b_mm_mmu_fault_handle_mmu_fault_common,
+ *          gv11b_mm_mmu_fault_handle_mmu_fault_ce,
+ *          gv11b_mm_mmu_fault_handle_non_replayable,
+ *          gv11b_mm_mmu_fault_handle_mmu_fault_refch
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Check that fault handler processes valid and invalid cases of mmu fault.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_handle_mmu_fault_common(struct unit_module *m,
+					struct gk20a *g, void *args);
+
+/**
+ * Test specification for:
+ *
+ * Description: Test non-replayable replayable fault handler
+ *
+ * Test Type: Feature
+ *
+ * Targets: gv11b_mm_mmu_fault_handle_nonreplay_replay_fault,
+ *          gv11b_mm_mmu_fault_handle_buf_valid_entry,
+ *          gv11b_fb_copy_from_hw_fault_buf
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Test non-replayable fault handler with valid and invalid cases.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_handle_nonreplay_replay_fault(struct unit_module *m, struct gk20a *g,
+					void *args);
+
+/**
+ * Test specification for: test_env_clean_mm_mmu_fault_gv11b_fusa
+ *
+ * Description: Cleanup test environment
+ *
+ * Test Type: Feature
+ *
+ * Targets: None
+ *
+ * Input: test_env_init
+ *
+ * Steps:
+ * - Destroy memory and VMs initialized for the test.
+ *
+ * Output: Returns SUCCESS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+int test_env_clean_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
+					struct gk20a *g, void *args);
+
+/** @} */
+#endif /* UNIT_MM_HAL_MMU_FAULT_GV11B_FUSA_H */