diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 180ffc4ab..6c6953966 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -1,5 +1,6 @@ -/* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. +// SPDX-License-Identifier: MIT +/* SPDX-FileCopyrightText: Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES. + * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -432,6 +433,25 @@ static void nvgpu_profiler_disable_cau_and_smpc(struct gk20a *g) } } +static void nvgpu_profiler_init_pmasys_state(struct gk20a *g, + u32 gr_instance_id) +{ + /* Once MIG support gets added to Profiler, + * gr_instance_id will get consumed + */ + (void)gr_instance_id; + + nvgpu_log(g, gpu_dbg_prof, "HWPM PMA being reset"); + + if (g->ops.perf.reset_hwpm_pma_registers != NULL) { + g->ops.perf.reset_hwpm_pma_registers(g); + } + + if (g->ops.perf.reset_hwpm_pma_trigger_registers != NULL) { + g->ops.perf.reset_hwpm_pma_trigger_registers(g); + } +} + static int nvgpu_profiler_quiesce_hwpm_streamout_resident(struct gk20a *g, u32 gr_instance_id, void *pma_bytes_available_buffer_cpuva, @@ -586,6 +606,8 @@ static int nvgpu_profiler_quiesce_hwpm_streamout(struct gk20a *g, void *pma_bytes_available_buffer_cpuva, bool smpc_reserved) { + nvgpu_profiler_init_pmasys_state(g, gr_instance_id); + if (!is_ctxsw) { return nvgpu_profiler_quiesce_hwpm_streamout_resident(g, gr_instance_id, @@ -650,6 +672,10 @@ int nvgpu_profiler_unbind_hwpm_streamout(struct gk20a *g, return err; } + if (g->ops.perf.reset_pmasys_channel_registers != NULL) { + g->ops.perf.reset_pmasys_channel_registers(g); + } + err = nvgpu_profiler_unbind_hwpm(g, gr_instance_id, is_ctxsw, tsg); if (err) { return err; diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index e62fc8a5d..ffa63fc2d 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1,8 +1,8 @@ -/* +// SPDX-License-Identifier: MIT +/* SPDX-FileCopyrightText: Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES. + * All rights reserved. * GA10B Tegra HAL interface * - * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. - * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation @@ -1623,6 +1623,9 @@ static const struct gops_perf ga10b_ops_perf = { .enable_hs_streaming = ga10b_perf_enable_hs_streaming, .reset_hs_streaming_credits = ga10b_perf_reset_hs_streaming_credits, .enable_pmasys_legacy_mode = ga10b_perf_enable_pmasys_legacy_mode, + .reset_hwpm_pma_registers = ga10b_perf_reset_hwpm_pma_registers, + .reset_hwpm_pma_trigger_registers = ga10b_perf_reset_hwpm_pma_trigger_registers, + .reset_pmasys_channel_registers = ga10b_perf_reset_pmasys_channel_registers, }; #endif diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c index 3c1c4e519..36fa3a67a 100644 --- a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c +++ b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c @@ -1,5 +1,7 @@ +// SPDX-License-Identifier: MIT /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES. + * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -803,3 +805,169 @@ void ga10b_perf_enable_pmasys_legacy_mode(struct gk20a *g, bool enable) nvgpu_writel(g, perf_pmasys_controlreg_r(), val); } + +void ga10b_perf_reset_hwpm_pma_registers(struct gk20a *g) +{ + u32 val = 0; + u32 i = 0; + + + for (i = 0U; i < perf_pmasys_trigger_config_user__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_trigger_config_user_r(i)); + + val = set_field(val, perf_pmasys_trigger_config_user_pma_pulse_m(), + perf_pmasys_trigger_config_user_pma_pulse_disable_f()); + val = set_field(val, perf_pmasys_trigger_config_user_pma_pulse_window_m(), + perf_pmasys_trigger_config_user_pma_pulse_window_inside_f()); + val = set_field(val, perf_pmasys_trigger_config_user_pma_pulse_source_m(), + perf_pmasys_trigger_config_user_pma_pulse_source_internal_f()); + val = set_field(val, perf_pmasys_trigger_config_user_pma_pulse_cntr_m(), + perf_pmasys_trigger_config_user_pma_pulse_cntr_one_f()); + val = set_field(val, perf_pmasys_trigger_config_user_record_stream_m(), + perf_pmasys_trigger_config_user_record_stream_disable_f()); + + nvgpu_writel(g, perf_pmasys_trigger_config_user_r(i), val); + } + + for (i = 0U; i < perf_pmasys_config1__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_config1_r(i)); + + val = set_field(val, perf_pmasys_config1_bf_20_20_m(), + perf_pmasys_config1_bf_20_20_disable_f()); + val = set_field(val, perf_pmasys_config1_bf_21_21_m(), + perf_pmasys_config1_bf_21_21_enable_f()); + + nvgpu_writel(g, perf_pmasys_config1_r(i), val); + } + + for (i = 0U; i < perf_pmasys_config2__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_config2_r(i)); + + val = set_field(val, perf_pmasys_config2_bf_0_0_m(), + perf_pmasys_config2_bf_0_0_disable_f()); + + nvgpu_writel(g, perf_pmasys_config2_r(i), val); + } + + nvgpu_writel(g, perf_pmasys_pulse_timebaseset_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_pulse_timebasecnt_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_record_start_triggercnt_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_record_stop_triggercnt_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_record_total_triggercnt_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_trigger_global_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_router_config0_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_router_config1_r(), 0x0U); + + val = nvgpu_readl(g, perf_pmasys_controlb_r()); + val = set_field(val, perf_pmasys_controlb_coalesce_timeout_cycles_m(), + perf_pmasys_controlb_coalesce_timeout_cycles_64_f()); + val = set_field(val, perf_pmasys_controlb_mbu_cya_smb_m(), + perf_pmasys_controlb_mbu_cya_smb_disable_f()); + val = set_field(val, perf_pmasys_controlb_mbu_cya_ss_m(), + perf_pmasys_controlb_mbu_cya_ss_disable_f()); + val = set_field(val, perf_pmasys_controlb_keep_latest_m(), + perf_pmasys_controlb_keep_latest_disable_f()); + val = set_field(val, perf_pmasys_controlb_fault_nack_cya_m(), + perf_pmasys_controlb_fault_nack_cya_disable_f()); + nvgpu_writel(g, perf_pmasys_controlb_r(), val); +} + +void ga10b_perf_reset_hwpm_pma_trigger_registers(struct gk20a *g) +{ + nvgpu_writel(g, perf_pmasys_sys_trigger_start_mask_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_start_maskb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_stop_mask_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_stop_maskb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_config_tesla_mode_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_config_tesla_modeb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_config_mixed_mode_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_config_mixed_modeb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_start_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_startb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_status_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_sys_trigger_statusb_r(), 0x0U); + + nvgpu_writel(g, perf_pmasys_gpc_trigger_start_mask_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_start_maskb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_stop_mask_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_stop_maskb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_config_tesla_mode_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_config_tesla_modeb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_config_mixed_mode_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_config_mixed_modeb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_start_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_startb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_status_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_gpc_trigger_statusb_r(), 0x0U); + + nvgpu_writel(g, perf_pmasys_fbp_trigger_start_mask_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_start_maskb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_stop_mask_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_stop_maskb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_config_tesla_mode_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_config_tesla_modeb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_config_mixed_mode_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_config_mixed_modeb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_start_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_startb_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_status_r(), 0x0U); + nvgpu_writel(g, perf_pmasys_fbp_trigger_statusb_r(), 0x0U); +} + +void ga10b_perf_reset_pmasys_channel_registers(struct gk20a *g) +{ + u32 i = 0U; + u32 val = 0U; + + for (i = 0U; i < perf_pmasys_channel_config_user__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_channel_config_user_r(i)); + val = set_field(val, perf_pmasys_channel_config_user_keep_latest_m(), + perf_pmasys_channel_config_user_keep_latest_disable_f()); + val = set_field(val, perf_pmasys_channel_config_user_coalesce_timeout_cycles_m(), + perf_pmasys_channel_config_user_coalesce_timeout_cycles_64_f()); + nvgpu_writel(g, perf_pmasys_channel_config_user_r(i), val); + } + + for (i = 0U; i < perf_pmasys_config3__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_config3_r(i)); + val = set_field(val, perf_pmasys_config3_bf_1_1_m(), + perf_pmasys_config3_bf_1_1_disable_f()); + val = set_field(val, perf_pmasys_config3_bf_2_2_m(), + perf_pmasys_config3_bf_2_2_disable_f()); + val = set_field(val, perf_pmasys_config3_bf_3_3_m(), + perf_pmasys_config3_bf_3_3_disable_f()); + nvgpu_writel(g, perf_pmasys_config3_r(i), val); + } + + for (i = 0U; i < perf_pmasys_channel_control__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_channel_control_r(i)); + val = set_field(val, perf_pmasys_channel_control_stream_m(), + perf_pmasys_channel_control_stream_disable_f()); + val = set_field(val, perf_pmasys_channel_control_pmactxsw_mode_m(), + perf_pmasys_channel_control_pmactxsw_mode_enable_f()); + val = set_field(val, perf_pmasys_channel_control_pma_record_stream_m(), + perf_pmasys_channel_control_pma_record_stream_disable_f()); + val = set_field(val, perf_pmasys_channel_control_fe2all_ctxsw_freeze_enable_m(), + perf_pmasys_channel_control_fe2all_ctxsw_freeze_enable_true_f()); + val = set_field(val, perf_pmasys_channel_control_pma_ctxsw_freeze_m(), + perf_pmasys_channel_control_pma_ctxsw_freeze_false_f()); + nvgpu_writel(g, perf_pmasys_channel_control_r(i), val); + } + + for (i = 0U; i < perf_pmasys_channel_control_user__size_1_v(); i++) { + val = nvgpu_readl(g, perf_pmasys_channel_control_user_r(i)); + val = set_field(val, perf_pmasys_channel_control_user_stream_m(), + perf_pmasys_channel_control_user_stream_disable_f()); + val = set_field(val, perf_pmasys_channel_control_user_membuf_clear_status_m(), + perf_pmasys_channel_control_user_membuf_clear_status_init_f()); + val = set_field(val, perf_pmasys_channel_control_user_flush_coalesce_fifo_m(), + perf_pmasys_channel_control_user_flush_coalesce_fifo_init_f()); + val = set_field(val, perf_pmasys_channel_control_user_send_bind_m(), + perf_pmasys_channel_control_user_send_bind_init_f()); + val = set_field(val, perf_pmasys_channel_control_user_reset_data_fifo_m(), + perf_pmasys_channel_control_user_reset_data_fifo_init_f()); + val = set_field(val, perf_pmasys_channel_control_user_update_bytes_m(), + perf_pmasys_channel_control_user_update_bytes_init_f()); + nvgpu_writel(g, perf_pmasys_channel_control_user_r(i), val); + } +} diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h index f9ea9e821..c34673686 100644 --- a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h +++ b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.h @@ -1,5 +1,7 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES. + * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -68,6 +70,9 @@ int ga10b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed, void ga10b_perf_enable_hs_streaming(struct gk20a *g, bool enable); void ga10b_perf_reset_hs_streaming_credits(struct gk20a *g); void ga10b_perf_enable_pmasys_legacy_mode(struct gk20a *g, bool enable); +void ga10b_perf_reset_hwpm_pma_registers(struct gk20a *g); +void ga10b_perf_reset_hwpm_pma_trigger_registers(struct gk20a *g); +void ga10b_perf_reset_pmasys_channel_registers(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h index 8723581bf..c2c54ff85 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h @@ -1,5 +1,7 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES. + * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -115,6 +117,9 @@ struct gops_perf { void (*reset_hs_streaming_credits)(struct gk20a *g); void (*enable_pmasys_legacy_mode)(struct gk20a *g, bool enable); #endif + void (*reset_hwpm_pma_registers)(struct gk20a *g); + void (*reset_hwpm_pma_trigger_registers)(struct gk20a *g); + void (*reset_pmasys_channel_registers)(struct gk20a *g); }; struct gops_perfbuf { int (*perfbuf_enable)(struct gk20a *g, u64 offset, u32 size); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h index 418e7f3ef..9c75eaabb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h @@ -1,5 +1,7 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023, NVIDIA CORPORATION & AFFILIATES. + * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -80,7 +82,18 @@ #define perf_pmasys_channel_control_user_stream_disable_f() (0x0U) #define perf_pmasys_channel_control_user_update_bytes_m() (U32(0x1U) << 31U) #define perf_pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U) +#define perf_pmasys_channel_control_user_update_bytes_init_f() (0x0U) +#define perf_pmasys_channel_control_user_membuf_clear_status_m()\ + (U32(0x1U) << 1U) #define perf_pmasys_channel_control_user_membuf_clear_status_doit_f() (0x2U) +#define perf_pmasys_channel_control_user_membuf_clear_status_init_f() (0x0U) +#define perf_pmasys_channel_control_user_flush_coalesce_fifo_m()\ + (U32(0x1U) << 2U) +#define perf_pmasys_channel_control_user_flush_coalesce_fifo_init_f() (0x0U) +#define perf_pmasys_channel_control_user_send_bind_m() (U32(0x1U) << 3U) +#define perf_pmasys_channel_control_user_send_bind_init_f() (0x0U) +#define perf_pmasys_channel_control_user_reset_data_fifo_m() (U32(0x1U) << 25U) +#define perf_pmasys_channel_control_user_reset_data_fifo_init_f() (0x0U) #define perf_pmasys_channel_status_secure_r(i)\ (nvgpu_safe_add_u32(0x0024a610U, nvgpu_safe_mult_u32((i), 384U))) #define perf_pmasys_channel_status_secure__size_1_v() (0x00000001U) @@ -133,6 +146,15 @@ #define perf_pmasys_controlb_r() (0x0024a070U) #define perf_pmasys_controlb_coalesce_timeout_cycles_m() (U32(0x7U) << 4U) #define perf_pmasys_controlb_coalesce_timeout_cycles__prod_f() (0x40U) +#define perf_pmasys_controlb_coalesce_timeout_cycles_64_f() (0x20U) +#define perf_pmasys_controlb_mbu_cya_smb_m() (U32(0x1U) << 0U) +#define perf_pmasys_controlb_mbu_cya_smb_disable_f() (0x0U) +#define perf_pmasys_controlb_mbu_cya_ss_m() (U32(0x1U) << 1U) +#define perf_pmasys_controlb_mbu_cya_ss_disable_f() (0x0U) +#define perf_pmasys_controlb_keep_latest_m() (U32(0x1U) << 2U) +#define perf_pmasys_controlb_keep_latest_disable_f() (0x0U) +#define perf_pmasys_controlb_fault_nack_cya_m() (U32(0x1U) << 3U) +#define perf_pmasys_controlb_fault_nack_cya_disable_f() (0x0U) #define perf_pmasys_channel_config_user_r(i)\ (nvgpu_safe_add_u32(0x0024a640U, nvgpu_safe_mult_u32((i), 384U))) #define perf_pmasys_channel_config_user__size_1_v() (0x00000001U) @@ -140,6 +162,9 @@ (U32(0x7U) << 4U) #define perf_pmasys_channel_config_user_coalesce_timeout_cycles__prod_f()\ (0x40U) +#define perf_pmasys_channel_config_user_coalesce_timeout_cycles_64_f() (0x20U) +#define perf_pmasys_channel_config_user_keep_latest_m() (U32(0x1U) << 2U) +#define perf_pmasys_channel_config_user_keep_latest_disable_f() (0x0U) #define perf_pmmsys_engine_sel_r(i)\ (nvgpu_safe_add_u32(0x0026006cU, nvgpu_safe_mult_u32((i), 512U))) #define perf_pmmsys_engine_sel__size_1_v() (0x0000000cU) @@ -173,4 +198,97 @@ #define perf_pmmgpcrouter_enginestatus_r() (0x00244010U) #define perf_pmmfbprouter_perfmonstatus_r() (0x00246014U) #define perf_pmmfbprouter_enginestatus_r() (0x00246010U) +#define perf_pmasys_trigger_config_user_r(i)\ + (nvgpu_safe_add_u32(0x0024a694U, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_trigger_config_user__size_1_v() (0x00000001U) +#define perf_pmasys_trigger_config_user_pma_pulse_m() (U32(0x1U) << 0U) +#define perf_pmasys_trigger_config_user_pma_pulse_disable_f() (0x0U) +#define perf_pmasys_trigger_config_user_pma_pulse_window_m() (U32(0x1U) << 1U) +#define perf_pmasys_trigger_config_user_pma_pulse_window_inside_f() (0x0U) +#define perf_pmasys_trigger_config_user_pma_pulse_source_m() (U32(0x3U) << 2U) +#define perf_pmasys_trigger_config_user_pma_pulse_source_internal_f() (0x0U) +#define perf_pmasys_trigger_config_user_pma_pulse_cntr_m() (U32(0x3U) << 4U) +#define perf_pmasys_trigger_config_user_pma_pulse_cntr_one_f() (0x0U) +#define perf_pmasys_trigger_config_user_record_stream_m() (U32(0x1U) << 6U) +#define perf_pmasys_trigger_config_user_record_stream_disable_f() (0x0U) +#define perf_pmasys_config1_r(i)\ + (nvgpu_safe_add_u32(0x0024a62cU, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_config1__size_1_v() (0x00000001U) +#define perf_pmasys_config1_bf_20_20_m() (U32(0x1U) << 20U) +#define perf_pmasys_config1_bf_20_20_disable_f() (0x100000U) +#define perf_pmasys_config1_bf_21_21_m() (U32(0x1U) << 21U) +#define perf_pmasys_config1_bf_21_21_enable_f() (0x200000U) +#define perf_pmasys_config2_r(i)\ + (nvgpu_safe_add_u32(0x0024a630U, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_config2__size_1_v() (0x00000001U) +#define perf_pmasys_config2_bf_0_0_m() (U32(0x1U) << 0U) +#define perf_pmasys_config2_bf_0_0_disable_f() (0x0U) +#define perf_pmasys_pulse_timebaseset_r() (0x0024a698U) +#define perf_pmasys_pulse_timebasecnt_r() (0x0024a69cU) +#define perf_pmasys_record_start_triggercnt_r() (0x0024a724U) +#define perf_pmasys_record_stop_triggercnt_r() (0x0024a728U) +#define perf_pmasys_record_total_triggercnt_r() (0x0024a72cU) +#define perf_pmasys_trigger_global_r() (0x0024a008U) +#define perf_pmasys_router_config0_r() (0x0024a68cU) +#define perf_pmasys_router_config1_r() (0x0024a690U) +#define perf_pmasys_config3_r(i)\ + (nvgpu_safe_add_u32(0x0024a63cU, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_config3__size_1_v() (0x00000001U) +#define perf_pmasys_config3_bf_1_1_m() (U32(0x1U) << 1U) +#define perf_pmasys_config3_bf_1_1_disable_f() (0x0U) +#define perf_pmasys_config3_bf_2_2_m() (U32(0x1U) << 2U) +#define perf_pmasys_config3_bf_2_2_disable_f() (0x0U) +#define perf_pmasys_config3_bf_3_3_m() (U32(0x1U) << 3U) +#define perf_pmasys_config3_bf_3_3_disable_f() (0x0U) +#define perf_pmasys_channel_control_r(i)\ + (nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U))) +#define perf_pmasys_channel_control__size_1_v() (0x00000001U) +#define perf_pmasys_channel_control_stream_m() (U32(0x1U) << 0U) +#define perf_pmasys_channel_control_stream_disable_f() (0x0U) +#define perf_pmasys_channel_control_pmactxsw_mode_m() (U32(0x1U) << 1U) +#define perf_pmasys_channel_control_pmactxsw_mode_enable_f() (0x0U) +#define perf_pmasys_channel_control_pma_record_stream_m() (U32(0x1U) << 8U) +#define perf_pmasys_channel_control_pma_record_stream_disable_f() (0x0U) +#define perf_pmasys_channel_control_fe2all_ctxsw_freeze_enable_m()\ + (U32(0x1U) << 22U) +#define perf_pmasys_channel_control_fe2all_ctxsw_freeze_enable_true_f()\ + (0x400000U) +#define perf_pmasys_channel_control_pma_ctxsw_freeze_m() (U32(0x1U) << 23U) +#define perf_pmasys_channel_control_pma_ctxsw_freeze_false_f() (0x0U) +#define perf_pmasys_sys_trigger_start_mask_r() (0x0024a66cU) +#define perf_pmasys_sys_trigger_start_maskb_r() (0x0024a670U) +#define perf_pmasys_sys_trigger_stop_mask_r() (0x0024a684U) +#define perf_pmasys_sys_trigger_stop_maskb_r() (0x0024a688U) +#define perf_pmasys_sys_trigger_config_tesla_mode_r() (0x0024a6b0U) +#define perf_pmasys_sys_trigger_config_tesla_modeb_r() (0x0024a6b4U) +#define perf_pmasys_sys_trigger_config_mixed_mode_r() (0x0024a6c8U) +#define perf_pmasys_sys_trigger_config_mixed_modeb_r() (0x0024a6ccU) +#define perf_pmasys_sys_trigger_start_r() (0x0024a6e0U) +#define perf_pmasys_sys_trigger_startb_r() (0x0024a6e4U) +#define perf_pmasys_sys_trigger_status_r() (0x0024a710U) +#define perf_pmasys_sys_trigger_statusb_r() (0x0024a714U) +#define perf_pmasys_gpc_trigger_start_mask_r() (0x0024a65cU) +#define perf_pmasys_gpc_trigger_start_maskb_r() (0x0024a660U) +#define perf_pmasys_gpc_trigger_stop_mask_r() (0x0024a674U) +#define perf_pmasys_gpc_trigger_stop_maskb_r() (0x0024a678U) +#define perf_pmasys_gpc_trigger_config_tesla_mode_r() (0x0024a6a0U) +#define perf_pmasys_gpc_trigger_config_tesla_modeb_r() (0x0024a6a4U) +#define perf_pmasys_gpc_trigger_config_mixed_mode_r() (0x0024a6b8U) +#define perf_pmasys_gpc_trigger_config_mixed_modeb_r() (0x0024a6bcU) +#define perf_pmasys_gpc_trigger_start_r() (0x0024a6d0U) +#define perf_pmasys_gpc_trigger_startb_r() (0x0024a6d4U) +#define perf_pmasys_gpc_trigger_status_r() (0x0024a700U) +#define perf_pmasys_gpc_trigger_statusb_r() (0x0024a704U) +#define perf_pmasys_fbp_trigger_start_mask_r() (0x0024a664U) +#define perf_pmasys_fbp_trigger_start_maskb_r() (0x0024a668U) +#define perf_pmasys_fbp_trigger_stop_mask_r() (0x0024a67cU) +#define perf_pmasys_fbp_trigger_stop_maskb_r() (0x0024a680U) +#define perf_pmasys_fbp_trigger_config_tesla_mode_r() (0x0024a6a8U) +#define perf_pmasys_fbp_trigger_config_tesla_modeb_r() (0x0024a6acU) +#define perf_pmasys_fbp_trigger_config_mixed_mode_r() (0x0024a6c0U) +#define perf_pmasys_fbp_trigger_config_mixed_modeb_r() (0x0024a6c4U) +#define perf_pmasys_fbp_trigger_start_r() (0x0024a6d8U) +#define perf_pmasys_fbp_trigger_startb_r() (0x0024a6dcU) +#define perf_pmasys_fbp_trigger_status_r() (0x0024a708U) +#define perf_pmasys_fbp_trigger_statusb_r() (0x0024a70cU) #endif