From a09142c23144c48959bcd1b9ffe07a2baf43632a Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 1 Aug 2019 10:39:17 -0400 Subject: [PATCH] gpu: nvgpu: priv_ring: fix CERT-C violations CERT-C Rule INT30-C Requires that unsigned integer operations do not wrap. Fix these violations by using the safe ops. JIRA NVGPU-3868 Change-Id: Ifc7396146d85b34d6bd04eb16675ab6234364b1b Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2166258 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Kumbhar Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../hal/priv_ring/priv_ring_gp10b_fusa.c | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c index c113e0152..dbe6089c7 100644 --- a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -167,19 +168,25 @@ void gp10b_priv_ring_isr(struct gk20a *g) if ((status1 & BIT32(gpc)) == 0U) { continue; } - gpc_offset = gpc * gpc_stride; + gpc_offset = nvgpu_safe_mult_u32(gpc, gpc_stride); error_info = nvgpu_readl(g, - pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc_offset); + nvgpu_safe_add_u32( + pri_ringstation_gpc_gpc0_priv_error_info_r(), + gpc_offset)); error_code = nvgpu_readl(g, - pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc_offset); + nvgpu_safe_add_u32( + pri_ringstation_gpc_gpc0_priv_error_code_r(), + gpc_offset)); nvgpu_err(g, "GPC%u write error. ADR 0x%08x " "WRDAT 0x%08x " "INFO 0x%08x (subid 0x%08x priv level %d), " "CODE 0x%08x", gpc, - nvgpu_readl(g, - pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc_offset), - nvgpu_readl(g, - pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc_offset), + nvgpu_readl(g, nvgpu_safe_add_u32( + pri_ringstation_gpc_gpc0_priv_error_adr_r(), + gpc_offset)), + nvgpu_readl(g, nvgpu_safe_add_u32( + pri_ringstation_gpc_gpc0_priv_error_wrdat_r(), + gpc_offset)), error_info, pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info), pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info),