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gpu: nvgpu: Move gk20a_init_mm_setup_hw to common/mm/mm.c

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Move the gk20a_init_mm_setup_hw to common code. This function just
calls HALs to initialize various bits of HW. However, since this
code assumes that (some of) the HALs are present this code is treated
as a vGPU HAL (that is it's NULL for vGPU).

This patch also renames the MM HW init HAL.

Sicne the gv11b variant of this setup_hw HAL did have some differences
from the gk20a version the new common version required some work. The
gv11b code was copied into the common function but now the gv11b
specific calls were HAL'ified (since they will need to be anyway for
the MMU fault buf code) and protected by an if-condition.

JIRA NVGPU-2042

Change-Id: I959293394ee8793923d858ee37b7ce346096654f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104541
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2019-04-23 14:42:23 -07:00
committed by mobile promotions
parent 7633cf41fb
commit a0da2dee0f
16 changed files with 94 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
drivers/gpu/nvgpu/common/mm/mm.c
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@@ -562,6 +562,17 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
return err;
}
/*
* Some chips support replayable MMU faults. For such chips make sure
* SW is initialized.
*/
if (g->ops.mm.mmu_fault.setup_sw != NULL) {
err = g->ops.mm.mmu_fault.setup_sw(g);
if (err != 0) {
return err;
}
}
mm->remove_support = nvgpu_remove_mm_support;
mm->remove_ce_support = nvgpu_remove_mm_ce_support;
@@ -591,6 +602,52 @@ static int nvgpu_init_mm_pdb_cache_war(struct gk20a *g)
return 0;
}
/*
* Called through the HAL to handle vGPU: the vGPU doesn't have HW to initialize
* here.
*/
int nvgpu_mm_setup_hw(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
int err;
nvgpu_log_fn(g, " ");
if (g->ops.fb.set_mmu_page_size != NULL) {
g->ops.fb.set_mmu_page_size(g);
}
if (g->ops.fb.set_use_full_comp_tag_line != NULL) {
mm->use_full_comp_tag_line =
g->ops.fb.set_use_full_comp_tag_line(g);
}
g->ops.fb.init_hw(g);
if (g->ops.bus.bar1_bind != NULL) {
g->ops.bus.bar1_bind(g, &mm->bar1.inst_block);
}
if (g->ops.bus.bar2_bind != NULL) {
err = g->ops.bus.bar2_bind(g, &mm->bar2.inst_block);
if (err != 0) {
return err;
}
}
if (g->ops.mm.cache.fb_flush(g) != 0 ||
g->ops.mm.cache.fb_flush(g) != 0) {
return -EBUSY;
}
if (g->ops.mm.mmu_fault.setup_hw != NULL) {
g->ops.mm.mmu_fault.setup_hw(g);
}
nvgpu_log_fn(g, "done");
return 0;
}
int nvgpu_init_mm_support(struct gk20a *g)
{
int err;
@@ -610,8 +667,8 @@ int nvgpu_init_mm_support(struct gk20a *g)
return err;
}
if (g->ops.mm.init_mm_setup_hw != NULL) {
err = g->ops.mm.init_mm_setup_hw(g);
if (g->ops.mm.setup_hw != NULL) {
err = g->ops.mm.setup_hw(g);
}
return err;