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gpu: nvgpu: add refcounting for MMU debug mode
GPC MMU debug mode should be set if at least one channel in the TSG has requested it. Add refcounting for MMU debug mode, to make sure debug mode is disabled only when no channel in the TSG is using it. Bug 2515097 Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123017 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -215,6 +215,14 @@ int nvgpu_tsg_unbind_channel_common(struct nvgpu_tsg *tsg,
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g->ops.channel.disable(ch);
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nvgpu_rwsem_up_write(&tsg->ch_list_lock);
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if (ch->mmu_debug_mode_enabled) {
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err = nvgpu_tsg_set_mmu_debug_mode(tsg, ch, false);
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if (err != 0) {
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nvgpu_err(g, "disable mmu debug mode failed ch:%u",
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ch->chid);
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}
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}
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/*
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* Don't re-enable all channels if TSG has timed out already
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*
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@@ -876,3 +884,49 @@ void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg,
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}
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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}
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int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg,
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struct nvgpu_channel *ch, bool enable)
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{
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struct gk20a *g;
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int err = 0;
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u32 tsg_refcnt;
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if ((ch == NULL) || (tsg == NULL)) {
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return -EINVAL;
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}
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g = ch->g;
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if (g->ops.gr.set_mmu_debug_mode == NULL) {
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return -ENOSYS;
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}
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if (enable) {
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if (ch->mmu_debug_mode_enabled) {
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/* already enabled for this channel */
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return 0;
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}
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tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U;
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} else {
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if (!ch->mmu_debug_mode_enabled) {
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/* already disabled for this channel */
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return 0;
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}
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tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U;
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}
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/*
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* enable GPC MMU debug mode if it was requested for at
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* least one channel in the TSG
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*/
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err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U);
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if (err != 0) {
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nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
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return err;
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}
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ch->mmu_debug_mode_enabled = enable;
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tsg->mmu_debug_mode_refcnt = tsg_refcnt;
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return err;
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}
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