gpu: nvgpu: compile out vidmem from safety build

Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.

JIRA NVGPU-3524

Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/acr/acr.c

@@ -54,6 +54,7 @@ bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr,
 	return acr->lsf[falcon_id].is_lazy_bootstrap;
 }
 
+#ifdef CONFIG_NVGPU_DGPU
 int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr,
 	size_t size)
 {
@@ -69,6 +70,7 @@ int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr,
 
 	return acr->alloc_blob_space(g, size, &acr->ucode_blob);
 }
+#endif
 
 /* ACR blob construct & bootstrap */
 int nvgpu_acr_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr)

drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c

@@ -173,8 +173,10 @@ void nvgpu_gv100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
 	nvgpu_gv100_acr_default_sw_init(g, &acr->acr);
 
 	acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
+#ifdef CONFIG_NVGPU_DGPU
 	acr->get_wpr_info = nvgpu_acr_wpr_info_vid;
 	acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_vid;
+#endif
 	acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode;
 	acr->patch_wpr_info_to_ucode =
 		gv100_acr_patch_wpr_info_to_ucode;

drivers/gpu/nvgpu/common/cbc/cbc.c

@@ -85,6 +85,7 @@ int nvgpu_cbc_alloc(struct gk20a *g, size_t compbit_backing_size,
 		return 0;
 	}
 
+#ifdef CONFIG_NVGPU_DGPU
 	if (vidmem_alloc == true) {
 		/*
 		 * Backing store MUST be physically contiguous and allocated in
@@ -97,7 +98,9 @@ int nvgpu_cbc_alloc(struct gk20a *g, size_t compbit_backing_size,
 		return nvgpu_dma_alloc_vid(g,
 					 compbit_backing_size,
 					 &cbc->compbit_store.mem);
-	} else {
+	} else
+#endif
+	{
 		return nvgpu_dma_alloc_flags_sys(g,
 					 NVGPU_DMA_PHYSICALLY_ADDRESSED,
 					 compbit_backing_size,

drivers/gpu/nvgpu/common/ce/ce.c

@@ -36,6 +36,7 @@
 static inline u32 nvgpu_ce_get_valid_launch_flags(struct gk20a *g,
 		u32 launch_flags)
 {
+#ifdef CONFIG_NVGPU_DGPU
 	/*
 	 * there is no local memory available,
 	 * don't allow local memory related CE flags
@@ -44,6 +45,7 @@ static inline u32 nvgpu_ce_get_valid_launch_flags(struct gk20a *g,
 		launch_flags &= ~(NVGPU_CE_SRC_LOCATION_LOCAL_FB |
 			NVGPU_CE_DST_LOCATION_LOCAL_FB);
 	}
+#endif
 	return launch_flags;
 }
 

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -261,11 +261,12 @@ static void nvgpu_channel_usermode_deinit(struct nvgpu_channel *ch)
 
 static void nvgpu_channel_kernelmode_deinit(struct nvgpu_channel *ch)
 {
-	struct gk20a *g = ch->g;
 	struct vm_gk20a *ch_vm = ch->vm;
 
 	nvgpu_dma_unmap_free(ch_vm, &ch->gpfifo.mem);
-	nvgpu_big_free(g, ch->gpfifo.pipe);
+#ifdef CONFIG_NVGPU_DGPU
+	nvgpu_big_free(ch->g, ch->gpfifo.pipe);
+#endif
 	(void) memset(&ch->gpfifo, 0, sizeof(struct gpfifo_desc));
 
 	nvgpu_channel_free_priv_cmd_q(ch);
@@ -1307,6 +1308,7 @@ static int nvgpu_channel_setup_kernelmode(struct nvgpu_channel *c,
 		goto clean_up;
 	}
 
+#ifdef CONFIG_NVGPU_DGPU
 	if (c->gpfifo.mem.aperture == APERTURE_VIDMEM) {
 		c->gpfifo.pipe = nvgpu_big_malloc(g,
 					(size_t)gpfifo_size *
@@ -1316,6 +1318,7 @@ static int nvgpu_channel_setup_kernelmode(struct nvgpu_channel *c,
 			goto clean_up_unmap;
 		}
 	}
+#endif
 	gpfifo_gpu_va = c->gpfifo.mem.gpu_va;
 
 	c->gpfifo.entry_num = gpfifo_size;
@@ -1383,7 +1386,9 @@ clean_up_sync:
 		c->sync = NULL;
 	}
 clean_up_unmap:
+#ifdef CONFIG_NVGPU_DGPU
 	nvgpu_big_free(g, c->gpfifo.pipe);
+#endif
 	nvgpu_dma_unmap_free(c->vm, &c->gpfifo.mem);
 clean_up:
 	(void) memset(&c->gpfifo, 0, sizeof(struct gpfifo_desc));

drivers/gpu/nvgpu/common/fifo/submit.c

@@ -286,10 +286,13 @@ static int nvgpu_submit_append_gpfifo(struct nvgpu_channel *c,
 		struct nvgpu_gpfifo_userdata userdata,
 		u32 num_entries)
 {
-	struct gk20a *g = c->g;
 	int err;
 
-	if ((kern_gpfifo == NULL) && (c->gpfifo.pipe == NULL)) {
+	if ((kern_gpfifo == NULL)
+#ifdef CONFIG_NVGPU_DGPU
+	    && (c->gpfifo.pipe == NULL)
+#endif
+	   ) {
 		/*
 		 * This path (from userspace to sysmem) is special in order to
 		 * avoid two copies unnecessarily (from user to pipe, then from
@@ -300,17 +303,21 @@ static int nvgpu_submit_append_gpfifo(struct nvgpu_channel *c,
 		if (err != 0) {
 			return err;
 		}
-	} else if (kern_gpfifo == NULL) {
+	}
+#ifdef CONFIG_NVGPU_DGPU
+	else if (kern_gpfifo == NULL) {
 		/* from userspace to vidmem, use the common path */
-		err = g->os_channel.copy_user_gpfifo(c->gpfifo.pipe, userdata,
-				0, num_entries);
+		err = c->g->os_channel.copy_user_gpfifo(c->gpfifo.pipe,
+				userdata, 0, num_entries);
 		if (err != 0) {
 			return err;
 		}
 
 		nvgpu_submit_append_gpfifo_common(c, c->gpfifo.pipe,
 				num_entries);
-	} else {
+	}
+#endif
+	else {
 		/* from kernel to either sysmem or vidmem, don't need
 		 * copy_user_gpfifo so use the common path */
 		nvgpu_submit_append_gpfifo_common(c, kern_gpfifo, num_entries);

drivers/gpu/nvgpu/common/mm/allocators/nvgpu_allocator.c

@@ -190,10 +190,12 @@ int nvgpu_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
 		err = nvgpu_buddy_allocator_init(g, na, vm, name, base, length,
 						blk_size, max_order, flags);
 		break;
+#ifdef CONFIG_NVGPU_DGPU
 	case PAGE_ALLOCATOR:
 		err = nvgpu_page_allocator_init(g, na, name, base, length,
 							blk_size, flags);
 		break;
+#endif
 	case BITMAP_ALLOCATOR:
 		err = nvgpu_bitmap_allocator_init(g, na, name, base, length,
 							blk_size, flags);

drivers/gpu/nvgpu/common/mm/dma.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -35,6 +35,7 @@ int nvgpu_dma_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
 int nvgpu_dma_alloc_flags(struct gk20a *g, unsigned long flags, size_t size,
 		struct nvgpu_mem *mem)
 {
+#ifdef CONFIG_NVGPU_DGPU
 	if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) {
 		/*
 		 * Force the no-kernel-mapping flag on because we don't support
@@ -59,6 +60,7 @@ int nvgpu_dma_alloc_flags(struct gk20a *g, unsigned long flags, size_t size,
 		 * vidmem is exhausted.
 		 */
 	}
+#endif
 
 	return nvgpu_dma_alloc_flags_sys(g, flags, size, mem);
 }
@@ -68,6 +70,7 @@ int nvgpu_dma_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
 	return nvgpu_dma_alloc_flags_sys(g, 0, size, mem);
 }
 
+#ifdef CONFIG_NVGPU_DGPU
 int nvgpu_dma_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
 {
 	return nvgpu_dma_alloc_flags_vid(g,
@@ -86,6 +89,7 @@ int nvgpu_dma_alloc_vid_at(struct gk20a *g,
 	return nvgpu_dma_alloc_flags_vid_at(g,
 			NVGPU_DMA_NO_KERNEL_MAPPING, size, mem, at);
 }
+#endif
 
 int nvgpu_dma_alloc_map(struct vm_gk20a *vm, size_t size,
 		struct nvgpu_mem *mem)
@@ -96,6 +100,7 @@ int nvgpu_dma_alloc_map(struct vm_gk20a *vm, size_t size,
 int nvgpu_dma_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags,
 		size_t size, struct nvgpu_mem *mem)
 {
+#ifdef CONFIG_NVGPU_DGPU
 	if (!nvgpu_is_enabled(gk20a_from_vm(vm), NVGPU_MM_UNIFIED_MEMORY)) {
 		/*
 		 * Force the no-kernel-mapping flag on because we don't support
@@ -116,6 +121,7 @@ int nvgpu_dma_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags,
 		 * vidmem is exhausted.
 		 */
 	}
+#endif
 
 	return nvgpu_dma_alloc_map_flags_sys(vm, flags, size, mem);
 }
@@ -150,6 +156,7 @@ fail_free:
 	return err;
 }
 
+#ifdef CONFIG_NVGPU_DGPU
 int nvgpu_dma_alloc_map_vid(struct vm_gk20a *vm, size_t size,
 		struct nvgpu_mem *mem)
 {
@@ -180,6 +187,7 @@ fail_free:
 	nvgpu_dma_free(vm->mm->g, mem);
 	return err;
 }
+#endif
 
 void nvgpu_dma_free(struct gk20a *g, struct nvgpu_mem *mem)
 {
@@ -187,9 +195,11 @@ void nvgpu_dma_free(struct gk20a *g, struct nvgpu_mem *mem)
 	case APERTURE_SYSMEM:
 		nvgpu_dma_free_sys(g, mem);
 		break;
+#ifdef CONFIG_NVGPU_DGPU
 	case APERTURE_VIDMEM:
 		nvgpu_dma_free_vid(g, mem);
 		break;
+#endif
 	default:
 		/* like free() on "null" memory */
 		break;

drivers/gpu/nvgpu/common/mm/mm.c

@@ -41,7 +41,9 @@ int nvgpu_mm_suspend(struct gk20a *g)
 
 	nvgpu_log_info(g, "MM suspend running...");
 
+#ifdef CONFIG_NVGPU_DGPU
 	nvgpu_vidmem_thread_pause_sync(&g->mm);
+#endif
 
 #ifdef CONFIG_NVGPU_COMPRESSION
 	g->ops.mm.cache.cbc_clean(g);
@@ -114,6 +116,7 @@ static int nvgpu_alloc_sysmem_flush(struct gk20a *g)
 #ifdef CONFIG_NVGPU_CE
 static void nvgpu_remove_mm_ce_support(struct mm_gk20a *mm)
 {
+#ifdef CONFIG_NVGPU_DGPU
 	struct gk20a *g = gk20a_from_mm(mm);
 
 	if (mm->vidmem.ce_ctx_id != NVGPU_CE_INVAL_CTX_ID) {
@@ -122,6 +125,7 @@ static void nvgpu_remove_mm_ce_support(struct mm_gk20a *mm)
 	mm->vidmem.ce_ctx_id = NVGPU_CE_INVAL_CTX_ID;
 
 	nvgpu_vm_put(mm->ce.vm);
+#endif
 }
 #endif
 
@@ -162,7 +166,9 @@ static void nvgpu_remove_mm_support(struct mm_gk20a *mm)
 	}
 
 	nvgpu_semaphore_sea_destroy(g);
+#ifdef CONFIG_NVGPU_DGPU
 	nvgpu_vidmem_destroy(g);
+#endif
 	nvgpu_pd_cache_fini(g);
 
 	if (g->ops.ramin.deinit_pdb_cache_war != NULL) {
@@ -297,7 +303,7 @@ static int nvgpu_init_mmu_debug(struct mm_gk20a *mm)
 #ifdef CONFIG_NVGPU_CE
 void nvgpu_init_mm_ce_context(struct gk20a *g)
 {
-#if defined(CONFIG_GK20A_VIDMEM)
+#if defined(CONFIG_NVGPU_DGPU)
 	if (g->mm.vidmem.size > 0U &&
 	   (g->mm.vidmem.ce_ctx_id == NVGPU_CE_INVAL_CTX_ID)) {
 		g->mm.vidmem.ce_ctx_id =
@@ -421,10 +427,11 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
 		   U32(mm->channel.user_size >> U64(20)),
 		   U32(mm->channel.kernel_size >> U64(20)));
 
-	nvgpu_init_pramin(mm);
-
+#ifdef CONFIG_NVGPU_DGPU
 	mm->vidmem.ce_ctx_id = NVGPU_CE_INVAL_CTX_ID;
 
+	nvgpu_init_pramin(mm);
+
 	err = nvgpu_vidmem_init(mm);
 	if (err != 0) {
 		return err;
@@ -441,6 +448,7 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
 			return err;
 		}
 	}
+#endif
 
 	err = nvgpu_alloc_sysmem_flush(g);
 	if (err != 0) {

drivers/gpu/nvgpu/common/mm/nvgpu_mem.c

@@ -44,6 +44,7 @@ u32 nvgpu_aperture_mask_raw(struct gk20a *g, enum nvgpu_aperture aperture,
 		nvgpu_do_assert_print(g, "Bad aperture");
 		return 0;
 	}
+
 	/*
 	 * Some iGPUs treat sysmem (i.e SoC DRAM) as vidmem. In these cases the
 	 * "sysmem" aperture should really be translated to VIDMEM.
@@ -96,7 +97,9 @@ bool nvgpu_mem_is_sysmem(struct nvgpu_mem *mem)
 u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys)
 {
 	/* ensure it is not vidmem allocation */
+#ifdef CONFIG_NVGPU_DGPU
 	WARN_ON(nvgpu_addr_is_vidmem_page_alloc(phys));
+#endif
 
 	if (nvgpu_iommuable(g) && g->ops.mm.gmmu.get_iommu_bit != NULL) {
 		return phys | 1ULL << g->ops.mm.gmmu.get_iommu_bit(g);
@@ -114,10 +117,14 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
 
 		WARN_ON(ptr == NULL);
 		data = ptr[w];
-	} else if (mem->aperture == APERTURE_VIDMEM) {
+	}
+#ifdef CONFIG_NVGPU_DGPU
+	else if (mem->aperture == APERTURE_VIDMEM) {
 		nvgpu_pramin_rd_n(g, mem, w * (u32)sizeof(u32),
 				(u32)sizeof(u32), &data);
-	} else {
+	}
+#endif
+	else {
 		nvgpu_do_assert_print(g, "Accessing unallocated nvgpu_mem");
 	}
 
@@ -149,9 +156,13 @@ void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
 
 		WARN_ON(mem->cpu_va == NULL);
 		nvgpu_memcpy((u8 *)dest, src, size);
-	} else if (mem->aperture == APERTURE_VIDMEM) {
+	}
+#ifdef CONFIG_NVGPU_DGPU
+	else if (mem->aperture == APERTURE_VIDMEM) {
 		nvgpu_pramin_rd_n(g, mem, offset, size, dest);
-	} else {
+	}
+#endif
+	else {
 		nvgpu_do_assert_print(g, "Accessing unallocated nvgpu_mem");
 	}
 }
@@ -163,13 +174,17 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
 
 		WARN_ON(ptr == NULL);
 		ptr[w] = data;
-	} else if (mem->aperture == APERTURE_VIDMEM) {
+	}
+#ifdef CONFIG_NVGPU_DGPU
+	else if (mem->aperture == APERTURE_VIDMEM) {
 		nvgpu_pramin_wr_n(g, mem, w * (u32)sizeof(u32),
 				  (u32)sizeof(u32), &data);
 		if (!mem->skip_wmb) {
 			nvgpu_wmb();
 		}
-	} else {
+	}
+#endif
+	else {
 		nvgpu_do_assert_print(g, "Accessing unallocated nvgpu_mem");
 	}
 }
@@ -191,12 +206,16 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 
 		WARN_ON(mem->cpu_va == NULL);
 		nvgpu_memcpy(dest, (u8 *)src, size);
-	} else if (mem->aperture == APERTURE_VIDMEM) {
+	}
+#ifdef CONFIG_NVGPU_DGPU
+	else if (mem->aperture == APERTURE_VIDMEM) {
 		nvgpu_pramin_wr_n(g, mem, offset, size, src);
 		if (!mem->skip_wmb) {
 			nvgpu_wmb();
 		}
-	} else {
+	}
+#endif
+	else {
 		nvgpu_do_assert_print(g, "Accessing unallocated nvgpu_mem");
 	}
 }
@@ -215,14 +234,18 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
 
 		WARN_ON(mem->cpu_va == NULL);
 		(void) memset(dest, (int)c, size);
-	} else if (mem->aperture == APERTURE_VIDMEM) {
+	}
+#ifdef CONFIG_NVGPU_DGPU
+	else if (mem->aperture == APERTURE_VIDMEM) {
 		u32 repeat_value = c | (c << 8) | (c << 16) | (c << 24);
 
 		nvgpu_pramin_memset(g, mem, offset, size, repeat_value);
 		if (!mem->skip_wmb) {
 			nvgpu_wmb();
 		}
-	} else {
+	}
+#endif
+	else {
 		nvgpu_do_assert_print(g, "Accessing unallocated nvgpu_mem");
 	}
 }

drivers/gpu/nvgpu/common/pmu/ipc/pmu_cmd.c

@@ -213,11 +213,16 @@ static int pmu_payload_allocate(struct gk20a *g, struct pmu_sequence *seq,
 			goto clean_up;
 		}
 
+#ifdef CONFIG_NVGPU_DGPU
 		err = nvgpu_pmu_vidmem_surface_alloc(g, alloc->fb_surface,
 						     alloc->fb_size);
 		if (err != 0) {
 			goto clean_up;
 		}
+#else
+		err = -ENOMEM;
+		goto clean_up;
+#endif
 	}
 
 	if (nvgpu_pmu_fb_queue_enabled(&pmu->queues)) {

drivers/gpu/nvgpu/common/pmu/pmu_allocator.c

@@ -72,6 +72,7 @@ void nvgpu_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
 	fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24U);
 }
 
+#ifdef CONFIG_NVGPU_DGPU
 int nvgpu_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
 		u32 size)
 {
@@ -87,6 +88,7 @@ int nvgpu_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
 
 	return 0;
 }
+#endif
 
 int nvgpu_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
 		u32 size)

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -619,9 +619,11 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 			.get_mmu_levels = gp10b_mm_get_mmu_levels,
 		},
 	},
+#ifdef CONFIG_NVGPU_DGPU
 	.pramin = {
 		.data032_r = NULL,
 	},
+#endif
 	.therm = {
 		.init_therm_setup_hw = NULL,
 		.init_elcg_mode = NULL,
@@ -737,7 +739,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.isr = NULL,
 		.bar1_bind = NULL,
 		.bar2_bind = NULL,
+#ifdef CONFIG_NVGPU_DGPU
 		.set_bar0_window = NULL,
+#endif
 	},
 	.ptimer = {
 		.isr = NULL,
@@ -816,7 +820,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	gops->pbdma_status = vgpu_gp10b_ops.pbdma_status;
 	gops->netlist = vgpu_gp10b_ops.netlist;
 	gops->mm = vgpu_gp10b_ops.mm;
+#ifdef CONFIG_NVGPU_DGPU
 	gops->pramin = vgpu_gp10b_ops.pramin;
+#endif
 	gops->therm = vgpu_gp10b_ops.therm;
 #ifdef CONFIG_NVGPU_LS_PMU
 	gops->pmu = vgpu_gp10b_ops.pmu;

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -834,7 +834,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.isr = NULL,
 		.bar1_bind = NULL,
 		.bar2_bind = NULL,
+#ifdef CONFIG_NVGPU_DGPU
 		.set_bar0_window = NULL,
+#endif
 	},
 	.ptimer = {
 		.isr = NULL,