diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 20fb51e72..e03c5da82 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1450,7 +1450,9 @@ bool gk20a_fifo_error_tsg(struct gk20a *g,
 	nvgpu_rwsem_down_read(&tsg->ch_list_lock);
 	nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
 		if (gk20a_channel_get(ch)) {
-			verbose |= gk20a_fifo_error_ch(g, ch);
+			if (gk20a_fifo_error_ch(g, ch)) {
+				verbose = true;
+			}
 			gk20a_channel_put(ch);
 		}
 	}
@@ -2291,7 +2293,9 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
 			if (gk20a_channel_get(ch)) {
 				ch->g->ops.fifo.set_error_notifier(ch,
 					NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
-				*verbose |= ch->timeout_debug_dump;
+				if (ch->timeout_debug_dump) {
+					*verbose = true;
+				}
 				gk20a_channel_put(ch);
 			}
 		}
@@ -2400,9 +2404,9 @@ static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr)
 	}
 
 	if (fifo_intr & fifo_intr_0_mmu_fault_pending_f()) {
-		print_channel_reset_log |=
-			gk20a_fifo_handle_mmu_fault(g, 0,
-					 ~(u32)0, false);
+		if (gk20a_fifo_handle_mmu_fault(g, 0, ~(u32)0, false)) {
+			print_channel_reset_log = true;
+		}
 		handled |= fifo_intr_0_mmu_fault_pending_f();
 	}
 
@@ -3241,8 +3245,9 @@ u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
 				skip_next = true;
 		}
 
-		if (!(*entries_left))
+		if (*entries_left == 0U) {
 			return NULL;
+		}
 
 		/* add TSG entry */
 		nvgpu_log_info(g, "add TSG %d to runlist", tsg->tsgid);
@@ -3261,7 +3266,7 @@ u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
 				      runlist->active_channels))
 				continue;
 
-			if (!(*entries_left)) {
+			if (*entries_left == 0U) {
 				nvgpu_rwsem_up_read(&tsg->ch_list_lock);
 				return NULL;
 			}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index ead5d34a8..39d6879ba 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5583,11 +5583,12 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
 		}
 	}
 
-	if (ignore_debugger)
+	if (ignore_debugger) {
 		nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
 			"ignore_debugger set, skipping event posting");
-	else
-		*post_event |= true;
+	} else {
+		*post_event = true;
+	}
 
 	return ret;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index cd3fe2f78..26ba944ae 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -404,7 +404,6 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
 			    u32 op_count)
 {
 	u32 i;
-	int err;
 	bool ok = true;
 	struct gk20a *g = dbg_s->g;
 
@@ -412,8 +411,9 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
 	 * a separate error code if needed */
 	for (i = 0; i < op_count; i++) {
 
-		err = validate_reg_op_info(dbg_s, &ops[i]);
-		ok &= !err;
+		if (validate_reg_op_info(dbg_s, &ops[i]) != 0) {
+			ok = false;
+		}
 
 		if (reg_op_is_gr_ctx(ops[i].type)) {
 			if (reg_op_is_read(ops[i].op))
@@ -424,8 +424,9 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
 
 		/* if "allow_all" flag enabled, dont validate offset */
 		if (!g->allow_all) {
-			err = validate_reg_op_offset(dbg_s, &ops[i]);
-			ok &= !err;
+			if (validate_reg_op_offset(dbg_s, &ops[i]) != 0) {
+				ok = false;
+			}
 		}
 	}