gpu: nvgpu: Get GA10B EMC floorsweeping status

The memory bandwidth reported by the nvgpu driver is a resultant of FBP and EMC floorsweeping status. The FBP floorsweep status was already getting reported in the GPU characterstics so the status of EMC was fetched and reported in this change.

Jira NVGPU-9609
Bug 3661074

Change-Id: Ia2fe6cb029d086765da15d9e964ea77256e06604
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859237
(cherry picked from commit 9dd2a8fc73)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2892943
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Tested-by: Kirill Artamonov <kartamonov@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.c

@@ -1,7 +1,7 @@
 /*
  * GA10B FUSE
  *
- * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -248,6 +248,32 @@ int ga10b_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
 	return 0;
 }
 
+u32 ga10b_fuse_status_opt_emc(struct gk20a *g)
+{
+	u32 fuse_val = 0;
+#ifdef __KERNEL__
+	/*
+	 * Read emc mask from fuse
+	 * Note that 0:enable and 1:disable in value read from fuse so we've to
+	 * flip the bits.
+	 * Also set unused bits to zero
+	 * Mapping of floorsweeping for MC/EMC based on channels,
+	 * bit[i] floorsweeps channels 4i to 4i+3, the full mapping is
+	 * opt_emc_disable[0]: channels 0-3, PD_emcba
+	 * opt_emc_disable[1]: channels 4-7, PD_emcbb
+	 * opt_emc_disable[2]: channels 8-11, PD_emcaa
+	 * opt_emc_disable[3]: channels 12-15, PD_emcab
+	 * The floorsweeping definition is a bitmap.
+	 */
+	nvgpu_tegra_fuse_read_opt_emc_disable(g, &fuse_val);
+	fuse_val = ~fuse_val;
+	fuse_val = fuse_val & nvgpu_safe_sub_u32(BIT32(4), 1U);
+#else
+	(void)g;
+#endif
+	return fuse_val;
+}
+
 u32 ga10b_fuse_opt_sec_debug_en(struct gk20a *g)
 {
 	return nvgpu_readl(g, fuse_opt_sec_debug_en_r());

drivers/gpu/nvgpu/hal/fuse/fuse_ga10b.h

@@ -1,7 +1,7 @@
 /*
  * GA10B FUSE
  *
- * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -47,6 +47,7 @@ void ga10b_fuse_read_feature_override_ecc(struct gk20a *g,
 		struct nvgpu_fuse_feature_override_ecc *ecc_feature);
 int ga10b_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi);
 u32 ga10b_fuse_opt_sec_debug_en(struct gk20a *g);
+u32 ga10b_fuse_status_opt_emc(struct gk20a *g);
 u32 ga10b_fuse_opt_secure_source_isolation_en(struct gk20a *g);
 int ga10b_fuse_check_priv_security(struct gk20a *g);
 int ga10b_fetch_falcon_fuse_settings(struct gk20a *g, u32 falcon_id,

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -1665,6 +1665,7 @@ static const struct gops_fuse ga10b_ops_fuse = {
 	.is_opt_feature_override_disable = ga10b_fuse_is_opt_feature_override_disable,
 	.fuse_status_opt_fbio = ga10b_fuse_status_opt_fbio,
 	.fuse_status_opt_fbp = ga10b_fuse_status_opt_fbp,
+	.fuse_status_opt_emc = ga10b_fuse_status_opt_emc,
 	.fuse_status_opt_l2_fbp = ga10b_fuse_status_opt_l2_fbp,
 	.fuse_status_opt_tpc_gpc = ga10b_fuse_status_opt_tpc_gpc,
 	.fuse_status_opt_pes_gpc = ga10b_fuse_status_opt_pes_gpc,

drivers/gpu/nvgpu/include/nvgpu/fuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -105,6 +105,19 @@ int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
  */
 int nvgpu_tegra_fuse_read_opt_gpc_disable(struct gk20a *g, u32 *val);
 
+/**
+ * @brief - Reads FUSE_OPT_EMC_DISABLE_0 fuse.
+ *
+ * @param g [in] - GPU super structure.
+ * @param val [out] - Populated with register FUSE_OPT_EMC_DISABLE_0 value.
+ *
+ * - Provide information about the SOC EMC floor-sweep info
+ *
+ * @return 0 on success or negative value on failure.
+ *
+ */
+int nvgpu_tegra_fuse_read_opt_emc_disable(struct gk20a *g, u32 *val);
+
 /**
  * @brief - Reads the per-device identifier fuses.
  *

drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -106,6 +106,18 @@ struct gops_fuse {
 	 */
 	u32 (*fuse_status_opt_fbp)(struct gk20a *g);
 
+	/**
+	 * @brief Read NV_FUSE_OPT_EMC_DISABLE_0 fuse.
+	 *
+	 * @param g [in]	The GPU driver struct.
+	 *
+	 * The HAL reads NV_FUSE_OPT_EMC_DISABLE_0 fuse value which provides EMC
+	 * floorsweeping status.
+	 *
+	 * @return fuse value read from NV_FUSE_OPT_EMC_DISABLE_0.
+	 */
+	u32 (*fuse_status_opt_emc)(struct gk20a *g);
+
 	/**
 	 * @brief Write NV_FUSE_CTRL_OPT_FBP fuse.
 	 *

drivers/gpu/nvgpu/include/nvgpu/linux/soc_fuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -27,6 +27,10 @@
 #define FUSE_OPT_GPC_DISABLE_0		0x188
 #endif
 
+#ifndef FUSE_OPT_EMC_DISABLE_0
+#define FUSE_OPT_EMC_DISABLE_0		0x8c0
+#endif
+
 #ifndef CONFIG_NVGPU_NVMEM_FUSE
 
 #ifndef FUSE_GCPLEX_CONFIG_FUSE_0

drivers/gpu/nvgpu/os/linux/fuse.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -48,6 +48,11 @@ int nvgpu_tegra_fuse_read_opt_gpc_disable(struct gk20a *g, u32 *val)
 	return tegra_fuse_readl(FUSE_OPT_GPC_DISABLE_0, val);
 }
 
+int nvgpu_tegra_fuse_read_opt_emc_disable(struct gk20a *g, u32 *val)
+{
+	return tegra_fuse_readl(FUSE_OPT_EMC_DISABLE_0, val);
+}
+
 int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
 {
 #ifdef CONFIG_NVGPU_NVMEM_FUSE

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2022, NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2011-2023, NVIDIA Corporation.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -492,6 +492,9 @@ static long gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.num_ltc = nvgpu_ltc_get_ltc_count(g);
 	gpu.lts_per_ltc = nvgpu_ltc_get_slices_per_ltc(g);
 	gpu.cbc_cache_line_size = nvgpu_ltc_get_cacheline_size(g);
+	if (g->ops.fuse.fuse_status_opt_emc) {
+		gpu.emc_en_mask = g->ops.fuse.fuse_status_opt_emc(g);
+	}
 
 	/*
 	 * TODO : Need to replace with proper HAL.

include/uapi/linux/nvgpu-ctrl.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -265,6 +265,7 @@ struct nvgpu_gpu_characteristics {
 
 	__u32 max_fbps_count;
 	__u32 fbp_en_mask;
+	__u32 emc_en_mask;
 	__u32 max_ltc_per_fbp;
 	__u32 max_lts_per_ltc;
 	__u32 max_tex_per_tpc;