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gpu: nvgpu: set graphics specific PRI values for graphics contexts

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Add new HAL gops.gr.init.set_default_gfx_regs() to set graphics specific
PRI values for graphics contexts in function nvgpu_gr_obj_ctx_alloc().

Add new HAL gops.gr.init.capture_gfx_regs() to capture and save init
values for the PRIs. Add new struct nvgpu_gr_obj_ctx_gfx_regs to hold the
PRI init values.

Define HAL functions gv11b_gr_init_set_default_gfx_regs() and
gv11b_gr_init_capture_gfx_regs(). Set the HAL functions for
gv11b and ga10b.

Register accessors required to set PRIs are auto-generated.

Bug 3506078

Change-Id: I4c2843a274f3c924e402541e600e104ed0c9ed1c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671598
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Jonathan Mccaffrey <jmccaffrey@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Deepak Nibade
2022-02-17 18:26:34 +05:30
committed by mobile promotions
parent e4cf52123f
commit a1ef716f9d
9 changed files with 179 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,6 +35,7 @@ struct gk20a;
struct nvgpu_gr_config;
struct nvgpu_gr_ctx;
struct netlist_av_list;
struct nvgpu_gr_obj_ctx_gfx_regs;
u32 gv11b_gr_init_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc,
struct nvgpu_gr_config *gr_config);
@@ -87,6 +88,10 @@ u32 gv11b_gr_init_get_patch_slots(struct gk20a *g,
struct nvgpu_gr_config *config);
void gv11b_gr_init_detect_sm_arch(struct gk20a *g);
void gv11b_gr_init_capture_gfx_regs(struct gk20a *g, struct nvgpu_gr_obj_ctx_gfx_regs *gfx_regs);
void gv11b_gr_init_set_default_gfx_regs(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
struct nvgpu_gr_obj_ctx_gfx_regs *gfx_regs);
#ifndef CONFIG_NVGPU_NON_FUSA
void gv11b_gr_init_set_default_compute_regs(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);

57
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
View File

@@ -37,6 +37,8 @@
#include "gr_init_gm20b.h"
#include "gr_init_gv11b.h"
#include "common/gr/obj_ctx_priv.h"
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
#ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
@@ -939,6 +941,61 @@ void gv11b_gr_init_detect_sm_arch(struct gk20a *g)
gr_gpc0_tpc0_sm_arch_warp_count_v(v);
}
void gv11b_gr_init_capture_gfx_regs(struct gk20a *g, struct nvgpu_gr_obj_ctx_gfx_regs *gfx_regs)
{
gfx_regs->reg_sm_disp_ctrl =
nvgpu_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
gfx_regs->reg_gpcs_setup_debug =
nvgpu_readl(g, gr_pri_gpcs_setup_debug_r());
gfx_regs->reg_tex_lod_dbg =
nvgpu_readl(g, gr_pri_gpcs_tpcs_tex_lod_dbg_r());
gfx_regs->reg_hww_warp_esr_report_mask =
nvgpu_readl(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r());
}
void gv11b_gr_init_set_default_gfx_regs(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
struct nvgpu_gr_obj_ctx_gfx_regs *gfx_regs)
{
u32 reg_val;
nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true);
reg_val = set_field(gfx_regs->reg_sm_disp_ctrl,
gr_gpcs_tpcs_sm_disp_ctrl_killed_ld_is_nop_m(),
gr_gpcs_tpcs_sm_disp_ctrl_killed_ld_is_nop_disable_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_sm_disp_ctrl_r(),
reg_val, true);
reg_val = set_field(gfx_regs->reg_gpcs_setup_debug,
gr_pri_gpcs_setup_debug_poly_offset_nan_is_zero_m(),
gr_pri_gpcs_setup_debug_poly_offset_nan_is_zero_enable_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pri_gpcs_setup_debug_r(),
reg_val, true);
reg_val = set_field(gfx_regs->reg_tex_lod_dbg,
gr_pri_gpcs_tpcs_tex_lod_dbg_cubeseam_aniso_m(),
gr_pri_gpcs_tpcs_tex_lod_dbg_cubeseam_aniso_enable_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pri_gpcs_tpcs_tex_lod_dbg_r(),
reg_val, true);
reg_val = set_field(gfx_regs->reg_hww_warp_esr_report_mask,
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_m(),
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_no_report_f());
reg_val = set_field(reg_val,
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_m(),
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_no_report_f());
reg_val = set_field(reg_val,
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_m(),
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_no_report_f());
reg_val = set_field(reg_val,
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_format_m(),
gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_tex_format_no_report_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(),
reg_val, true);
nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true);
}
#ifndef CONFIG_NVGPU_NON_FUSA
void gv11b_gr_init_set_default_compute_regs(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx)

2
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -645,6 +645,8 @@ static const struct gops_gr_init ga10b_ops_gr_init = {
.get_max_subctx_count = gv11b_gr_init_get_max_subctx_count,
.get_patch_slots = gv11b_gr_init_get_patch_slots,
.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
.capture_gfx_regs = gv11b_gr_init_capture_gfx_regs,
.set_default_gfx_regs = gv11b_gr_init_set_default_gfx_regs,
#ifndef CONFIG_NVGPU_NON_FUSA
.set_default_compute_regs = ga10b_gr_init_set_default_compute_regs,
#endif

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -536,6 +536,8 @@ static const struct gops_gr_init gv11b_ops_gr_init = {
.get_max_subctx_count = gv11b_gr_init_get_max_subctx_count,
.get_patch_slots = gv11b_gr_init_get_patch_slots,
.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
.capture_gfx_regs = gv11b_gr_init_capture_gfx_regs,
.set_default_gfx_regs = gv11b_gr_init_set_default_gfx_regs,
#ifndef CONFIG_NVGPU_NON_FUSA
.set_default_compute_regs = gv11b_gr_init_set_default_compute_regs,
#endif