From a232eb8d20565ecaee8f131022d4063475b7bffe Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Mon, 19 Aug 2019 16:43:20 +0530 Subject: [PATCH] gpu: nvgpu: fix PRE31-C violations in wpr/vpr dump nvgpu_err() macro with a nvgpu_readl() call results in a volatile access. This violates PRE31-C rule - "Using an unsafe function-like macro with side effect in argument nvgpu_readl()" due to side effect of a volatile access. Fix this by moving nvgpu_readl() calls before nvgpu_err(). The messages log VPR and WPR address info. There are no known attacks using this info. So it shall be safe to reveal address info. JIRA NVGPU-3908 Change-Id: I487a0c0858fe9a36cc81852cedd7757aab277c6a Signed-off-by: Nitin Kumbhar Reviewed-on: https://git-master.nvidia.com/r/2178416 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c | 32 ++++++++++++++++-------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c index 423a78b4c..1a6e7512d 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c @@ -212,35 +212,47 @@ u32 gm20b_fb_mmu_debug_rd(struct gk20a *g) void gm20b_fb_dump_vpr_info(struct gk20a *g) { u32 val; + u32 addr_lo, addr_hi, cya_lo, cya_hi; /* print vpr info */ val = gk20a_readl(g, fb_mmu_vpr_info_r()); val &= ~0x3U; val |= fb_mmu_vpr_info_index_addr_lo_v(); gk20a_writel(g, fb_mmu_vpr_info_r(), val); + + addr_lo = gk20a_readl(g, fb_mmu_vpr_info_r()); + addr_hi = gk20a_readl(g, fb_mmu_vpr_info_r()); + cya_lo = gk20a_readl(g, fb_mmu_vpr_info_r()); + cya_hi = gk20a_readl(g, fb_mmu_vpr_info_r()); + nvgpu_err(g, "VPR: %08x %08x %08x %08x", - gk20a_readl(g, fb_mmu_vpr_info_r()), - gk20a_readl(g, fb_mmu_vpr_info_r()), - gk20a_readl(g, fb_mmu_vpr_info_r()), - gk20a_readl(g, fb_mmu_vpr_info_r())); + addr_lo, addr_hi, cya_lo, cya_hi); } void gm20b_fb_dump_wpr_info(struct gk20a *g) { u32 val; + u32 allow_read, allow_write; + u32 wpr1_addr_lo, wpr1_addr_hi; + u32 wpr2_addr_lo, wpr2_addr_hi; /* print wpr info */ val = gk20a_readl(g, fb_mmu_wpr_info_r()); val &= ~0xfU; val |= (fb_mmu_wpr_info_index_allow_read_v()); gk20a_writel(g, fb_mmu_wpr_info_r(), val); + + allow_read = gk20a_readl(g, fb_mmu_wpr_info_r()); + allow_write = gk20a_readl(g, fb_mmu_wpr_info_r()); + wpr1_addr_lo = gk20a_readl(g, fb_mmu_wpr_info_r()); + wpr1_addr_hi = gk20a_readl(g, fb_mmu_wpr_info_r()); + wpr2_addr_lo = gk20a_readl(g, fb_mmu_wpr_info_r()); + wpr2_addr_hi = gk20a_readl(g, fb_mmu_wpr_info_r()); + nvgpu_err(g, "WPR: %08x %08x %08x %08x %08x %08x", - gk20a_readl(g, fb_mmu_wpr_info_r()), - gk20a_readl(g, fb_mmu_wpr_info_r()), - gk20a_readl(g, fb_mmu_wpr_info_r()), - gk20a_readl(g, fb_mmu_wpr_info_r()), - gk20a_readl(g, fb_mmu_wpr_info_r()), - gk20a_readl(g, fb_mmu_wpr_info_r())); + allow_read, allow_write, + wpr1_addr_lo, wpr1_addr_hi, + wpr2_addr_lo, wpr2_addr_hi); } static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g,