diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8d142566f..cceecf68b 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -330,6 +330,8 @@ nvgpu-y += \ common/ce2.o \ common/debugger.o \ common/nvlink/probe.o \ + common/nvlink/init/device_reginit_gv100.o \ + common/nvlink/init/device_reginit.o \ common/nvlink/nvlink.o \ common/nvlink/nvlink_gv100.o \ common/nvlink/nvlink_tu104.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index a9620bd72..88d8528a4 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -263,6 +263,8 @@ srcs += common/sim.c \ gv100/fifo_gv100.c \ gv100/gr_gv100.c \ common/nvlink/probe.c \ + common/nvlink/init/device_reginit.c \ + common/nvlink/init/device_reginit_gv100.c \ common/nvlink/nvlink_gv100.c \ common/nvlink/nvlink_tu104.c \ common/nvlink/nvlink.c \ diff --git a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c new file mode 100644 index 000000000..131ded7ea --- /dev/null +++ b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#ifdef CONFIG_TEGRA_NVLINK +int nvgpu_nvlink_reg_init(struct gk20a *g) +{ + int err; + + err = g->ops.nvlink.reg_init(g); + + return err; +} +#endif diff --git a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c new file mode 100644 index 000000000..d6231456e --- /dev/null +++ b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "device_reginit_gv100.h" + +#ifdef CONFIG_TEGRA_NVLINK +struct __nvlink_reginit { + u32 addr; + u32 value; +}; + +static const struct __nvlink_reginit __nvlink_reginit_per_link_tegra[] = { + /* NVTLC when connected to Tegra */ + { 0x300U, 0x00800040U }, + { 0x304U, 0x00000000U }, + { 0x308U, 0x00000000U }, + { 0x30CU, 0x00000000U }, + { 0x310U, 0x00000000U }, + { 0x314U, 0x00800040U }, + { 0x318U, 0x00000000U }, + { 0x31CU, 0x00000000U }, + { 0x200U, 0x007F003FU }, + { 0x204U, 0x007F003FU }, + { 0x208U, 0x007F003FU }, + { 0x20CU, 0x007F003FU }, + { 0x210U, 0x007F003FU }, + { 0x214U, 0x00FF007FU }, + { 0x218U, 0x00FF007FU }, + { 0x21CU, 0x00FF007FU }, + { 0xB00U, 0x010000C0U }, + { 0xB04U, 0x00000000U }, + { 0xB08U, 0x00000000U }, + { 0xB0CU, 0x00000000U }, + { 0xB10U, 0x00000000U }, + { 0xB14U, 0x010000C0U }, + { 0xB18U, 0x00000000U }, + { 0xB1CU, 0x00000000U }, + { 0xA00U, 0x00FF00BFU }, + { 0xA04U, 0x00FF00BFU }, + { 0xA08U, 0x00FF00BFU }, + { 0xA0CU, 0x00FF00BFU }, + { 0xA10U, 0x00FF00BFU }, + { 0xA14U, 0x01FF017FU }, + { 0xA18U, 0x01FF017FU }, + { 0xA1CU, 0x01FF017FU }, + { 0xF04U, 0x00FFFFFFU }, + { 0xF0CU, 0x00FFFFFFU }, + { 0xF1CU, 0x003FFFFFU }, + { 0xF24U, 0x003FFFFFU }, + { 0x704U, 0x003FFFFFU }, + { 0x70CU, 0x003FFFFFU }, + { 0x400U, 0x00000001U }, + { 0xC00U, 0x00000001U }, +}; + +static const struct __nvlink_reginit __nvlink_reginit_per_link_gpu[] = { + /* NVTLC for PEER GPU */ + { 0x300U, 0x00800040U }, + { 0x304U, 0x00000000U }, + { 0x308U, 0x00000000U }, + { 0x30CU, 0x00000000U }, + { 0x310U, 0x00000000U }, + { 0x314U, 0x00800040U }, + { 0x318U, 0x00000000U }, + { 0x31CU, 0x00000000U }, + { 0x200U, 0x007F003FU }, + { 0x204U, 0x007F003FU }, + { 0x208U, 0x007F003FU }, + { 0x20CU, 0x007F003FU }, + { 0x210U, 0x007F003FU }, + { 0x214U, 0x00FF007FU }, + { 0x218U, 0x00FF007FU }, + { 0x21CU, 0x00FF007FU }, + { 0xB00U, 0x010000C0U }, + { 0xB04U, 0x00000000U }, + { 0xB08U, 0x00000000U }, + { 0xB0CU, 0x00000000U }, + { 0xB10U, 0x00000000U }, + { 0xB14U, 0x010000C0U }, + { 0xB18U, 0x00000000U }, + { 0xB1CU, 0x00000000U }, + { 0xA00U, 0x00FF00BFU }, + { 0xA04U, 0x00FF00BFU }, + { 0xA08U, 0x00FF00BFU }, + { 0xA0CU, 0x00FF00BFU }, + { 0xA10U, 0x00FF00BFU }, + { 0xA14U, 0x01FF017FU }, + { 0xA18U, 0x01FF017FU }, + { 0xA1CU, 0x01FF017FU }, + { 0xF04U, 0x00FFFFFFU }, + { 0xF0CU, 0x00FFFFFFU }, + { 0xF1CU, 0x003FFFFFU }, + { 0xF24U, 0x003FFFFFU }, + { 0x704U, 0x003FFFFFU }, + { 0x70CU, 0x003FFFFFU }, + { 0x400U, 0x00000001U }, + { 0xC00U, 0x00000001U }, +}; + +static int gv100_nvlink_get_tlc_reginit(enum nvgpu_nvlink_endp endp, + struct __nvlink_reginit **reg, u32 *count) +{ + switch(endp) { + case nvgpu_nvlink_endp_tegra: + *reg = (struct __nvlink_reginit *) + __nvlink_reginit_per_link_tegra; + *count = ARRAY_SIZE(__nvlink_reginit_per_link_tegra); + break; + case nvgpu_nvlink_endp_gpu: + *reg = (struct __nvlink_reginit *) + __nvlink_reginit_per_link_gpu; + *count = ARRAY_SIZE(__nvlink_reginit_per_link_gpu); + break; + default: + return -EINVAL; + } + + return 0; +} + +int gv100_nvlink_reg_init(struct gk20a *g) +{ + u32 i = 0; + u32 count = 0; + struct __nvlink_reginit *reg; + enum nvgpu_nvlink_endp endp; + int err; + u32 link_id; + unsigned long mask = g->nvlink.enabled_links; + struct nvgpu_nvlink_link *link; + + /* Apply automated reg init flow for PROD settings */ + for_each_set_bit(link_id, &mask, 32) { + + link = &g->nvlink.links[link_id]; + if (!link->remote_info.is_connected) + continue; + + endp = link->remote_info.device_type; + err = gv100_nvlink_get_tlc_reginit(endp, ®, &count); + if (err != 0) { + nvgpu_err(g, "no reginit for endp=%u", endp); + continue; + } + + for (i = 0; i < count; i++) { + TLC_REG_WR32(g, link_id, reg->addr, reg->value); + reg++; + } + } + return 0; +} +#endif /* CONFIG_TEGRA_NVLINK */ diff --git a/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.h b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.h new file mode 100644 index 000000000..52a55cc24 --- /dev/null +++ b/drivers/gpu/nvgpu/common/nvlink/init/device_reginit_gv100.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DEVICE_REGINIT_GV100_H +#define DEVICE_REGINIT_GV100_H + +struct gk20a; + +int gv100_nvlink_reg_init(struct gk20a *g); + +#endif /* DEVICE_REGINIT_GV100_H */ diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c index f5db39198..1079eedb0 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c @@ -102,15 +102,6 @@ int nvgpu_nvlink_dev_shutdown(struct gk20a *g) return err; } -int nvgpu_nvlink_reg_init(struct gk20a *g) -{ - int err; - - err = g->ops.nvlink.reg_init(g); - - return err; -} - u32 nvgpu_nvlink_get_link_mode(struct gk20a *g) { u32 link_id; diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c index 50c0894b5..d62ad70c5 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c @@ -94,100 +94,6 @@ minion_falcon_irqdest_target_swgen0_host_normal_f() | \ minion_falcon_irqdest_target_swgen1_host_normal_f()) -struct __nvlink_reginit { - u32 addr; - u32 value; -}; - -static const struct __nvlink_reginit __nvlink_reginit_per_link_tegra[] = { - /* NVTLC when connected to Tegra */ - { 0x300U, 0x00800040U }, - { 0x304U, 0x00000000U }, - { 0x308U, 0x00000000U }, - { 0x30CU, 0x00000000U }, - { 0x310U, 0x00000000U }, - { 0x314U, 0x00800040U }, - { 0x318U, 0x00000000U }, - { 0x31CU, 0x00000000U }, - { 0x200U, 0x007F003FU }, - { 0x204U, 0x007F003FU }, - { 0x208U, 0x007F003FU }, - { 0x20CU, 0x007F003FU }, - { 0x210U, 0x007F003FU }, - { 0x214U, 0x00FF007FU }, - { 0x218U, 0x00FF007FU }, - { 0x21CU, 0x00FF007FU }, - { 0xB00U, 0x010000C0U }, - { 0xB04U, 0x00000000U }, - { 0xB08U, 0x00000000U }, - { 0xB0CU, 0x00000000U }, - { 0xB10U, 0x00000000U }, - { 0xB14U, 0x010000C0U }, - { 0xB18U, 0x00000000U }, - { 0xB1CU, 0x00000000U }, - { 0xA00U, 0x00FF00BFU }, - { 0xA04U, 0x00FF00BFU }, - { 0xA08U, 0x00FF00BFU }, - { 0xA0CU, 0x00FF00BFU }, - { 0xA10U, 0x00FF00BFU }, - { 0xA14U, 0x01FF017FU }, - { 0xA18U, 0x01FF017FU }, - { 0xA1CU, 0x01FF017FU }, - { 0xF04U, 0x00FFFFFFU }, - { 0xF0CU, 0x00FFFFFFU }, - { 0xF1CU, 0x003FFFFFU }, - { 0xF24U, 0x003FFFFFU }, - { 0x704U, 0x003FFFFFU }, - { 0x70CU, 0x003FFFFFU }, - { 0x400U, 0x00000001U }, - { 0xC00U, 0x00000001U }, -}; - -static const struct __nvlink_reginit __nvlink_reginit_per_link_gpu[] = { - /* NVTLC for PEER GPU */ - { 0x300U, 0x00800040U }, - { 0x304U, 0x00000000U }, - { 0x308U, 0x00000000U }, - { 0x30CU, 0x00000000U }, - { 0x310U, 0x00000000U }, - { 0x314U, 0x00800040U }, - { 0x318U, 0x00000000U }, - { 0x31CU, 0x00000000U }, - { 0x200U, 0x007F003FU }, - { 0x204U, 0x007F003FU }, - { 0x208U, 0x007F003FU }, - { 0x20CU, 0x007F003FU }, - { 0x210U, 0x007F003FU }, - { 0x214U, 0x00FF007FU }, - { 0x218U, 0x00FF007FU }, - { 0x21CU, 0x00FF007FU }, - { 0xB00U, 0x010000C0U }, - { 0xB04U, 0x00000000U }, - { 0xB08U, 0x00000000U }, - { 0xB0CU, 0x00000000U }, - { 0xB10U, 0x00000000U }, - { 0xB14U, 0x010000C0U }, - { 0xB18U, 0x00000000U }, - { 0xB1CU, 0x00000000U }, - { 0xA00U, 0x00FF00BFU }, - { 0xA04U, 0x00FF00BFU }, - { 0xA08U, 0x00FF00BFU }, - { 0xA0CU, 0x00FF00BFU }, - { 0xA10U, 0x00FF00BFU }, - { 0xA14U, 0x01FF017FU }, - { 0xA18U, 0x01FF017FU }, - { 0xA1CU, 0x01FF017FU }, - { 0xF04U, 0x00FFFFFFU }, - { 0xF0CU, 0x00FFFFFFU }, - { 0xF1CU, 0x003FFFFFU }, - { 0xF24U, 0x003FFFFFU }, - { 0x704U, 0x003FFFFFU }, - { 0x70CU, 0x003FFFFFU }, - { 0x400U, 0x00000001U }, - { 0xC00U, 0x00000001U }, -}; - - #define NVL_DEVICE(str) nvlinkip_discovery_common_device_##str##_v() static const char *__gv100_device_type_to_str(u32 type) @@ -756,27 +662,6 @@ static int gv100_nvlink_minion_lane_shutdown(struct gk20a *g, u32 link_id, *-----------------------------------------------------------------------------* */ -static int gv100_nvlink_get_tlc_reginit(enum nvgpu_nvlink_endp endp, - struct __nvlink_reginit **reg, u32 *count) -{ - switch(endp) { - case nvgpu_nvlink_endp_tegra: - *reg = (struct __nvlink_reginit *) - __nvlink_reginit_per_link_tegra; - *count = ARRAY_SIZE(__nvlink_reginit_per_link_tegra); - break; - case nvgpu_nvlink_endp_gpu: - *reg = (struct __nvlink_reginit *) - __nvlink_reginit_per_link_gpu; - *count = ARRAY_SIZE(__nvlink_reginit_per_link_gpu); - break; - default: - return -EINVAL; - } - - return 0; -} - /* * Init TLC IP and prod regs */ @@ -2033,39 +1918,6 @@ int gv100_nvlink_interface_disable(struct gk20a *g) return 0; } -int gv100_nvlink_reg_init(struct gk20a *g) -{ - u32 i = 0; - u32 count = 0; - struct __nvlink_reginit *reg; - enum nvgpu_nvlink_endp endp; - int err; - u32 link_id; - unsigned long mask = g->nvlink.enabled_links; - struct nvgpu_nvlink_link *link; - - /* Apply automated reg init flow for PROD settings */ - for_each_set_bit(link_id, &mask, 32) { - - link = &g->nvlink.links[link_id]; - if (!link->remote_info.is_connected) - continue; - - endp = link->remote_info.device_type; - err = gv100_nvlink_get_tlc_reginit(endp, ®, &count); - if (err != 0) { - nvgpu_err(g, "no reginit for endp=%u", endp); - continue; - } - - for (i = 0; i < count; i++) { - TLC_REG_WR32(g, link_id, reg->addr, reg->value); - reg++; - } - } - return 0; -} - /* * Shutdown device. This should tear down Nvlink connection. * For now return. diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h index 34d34f082..f2c531fa7 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -51,7 +51,6 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id, bool is_rx_sublink, u32 mode); int gv100_nvlink_interface_init(struct gk20a *g); int gv100_nvlink_interface_disable(struct gk20a *g); -int gv100_nvlink_reg_init(struct gk20a *g); int gv100_nvlink_shutdown(struct gk20a *g); int gv100_nvlink_early_init(struct gk20a *g); int gv100_nvlink_speed_config(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4240bcf14..bbf1181fc 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -68,6 +68,7 @@ #include "common/falcon/falcon_gk20a.h" #include "common/falcon/falcon_gv100.h" #include "common/nvdec/nvdec_gp106.h" +#include "common/nvlink/init/device_reginit_gv100.h" #include "common/nvlink/nvlink_gv100.h" #include "common/nvlink/nvlink_tu104.h" #include "common/pmu/perf/perf_gv100.h" diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h index 881cffb86..13732aff2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h @@ -233,7 +233,6 @@ int nvgpu_nvlink_link_early_init(struct gk20a *g); int nvgpu_nvlink_interface_init(struct gk20a *g); int nvgpu_nvlink_interface_disable(struct gk20a *g); int nvgpu_nvlink_dev_shutdown(struct gk20a *g); -int nvgpu_nvlink_reg_init(struct gk20a *g); u32 nvgpu_nvlink_get_link_mode(struct gk20a *g); u32 nvgpu_nvlink_get_link_state(struct gk20a *g); int nvgpu_nvlink_set_link_mode(struct gk20a *g, u32 mode); diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink_device_reginit.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink_device_reginit.h new file mode 100644 index 000000000..f89a3b52f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink_device_reginit.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_NVLINK_DEVICE_REGINIT_H +#define NVGPU_NVLINK_DEVICE_REGINIT_H + +struct gk20a; + +int nvgpu_nvlink_reg_init(struct gk20a *g); + +#endif /* NVGPU_NVLINK_DEVICE_REGINIT_H */ diff --git a/drivers/gpu/nvgpu/os/linux/nvlink_probe.c b/drivers/gpu/nvgpu/os/linux/nvlink_probe.c index c02b6207e..36ebd7e98 100644 --- a/drivers/gpu/nvgpu/os/linux/nvlink_probe.c +++ b/drivers/gpu/nvgpu/os/linux/nvlink_probe.c @@ -24,6 +24,7 @@ #include #include "module.h" #include +#include #ifdef CONFIG_TEGRA_NVLINK int nvgpu_nvlink_read_dt_props(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index ac7395d06..9da1eab90 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -74,6 +74,7 @@ #include "common/nvdec/nvdec_tu104.h" #include "common/top/top_gm20b.h" #include "common/top/top_gp10b.h" +#include "common/nvlink/init/device_reginit_gv100.h" #include "common/nvlink/nvlink_gv100.h" #include "common/nvlink/nvlink_tu104.h" #include "common/sync/syncpt_cmdbuf_gv11b.h"