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gpu: nvgpu: cbc: move cbc related code from gr

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Moved cbc related code and data from gr to cbc unit.

Ltc and cbc related data is moved from gr header:
1. Ltc related data moved from gr_gk20a -> gk20a and it
will be moved eventually to ltc unit:
u32 slices_per_ltc;
u32 cacheline_size;

2. cbc data moved from gr_gk20a -> nvgpu_cbc
u32 compbit_backing_size;
u32 comptags_per_cacheline;
u32 gobs_per_comptagline_per_slice;
u32 max_comptag_lines;
struct gk20a_comptag_allocator comp_tags;
struct compbit_store_desc compbit_store;

3. Following config data moved gr_gk20a -> gk20a
u32 comptag_mem_deduct;
u32 max_comptag_mem;
These are part of initial config which should be available
during nvgpu_probe. So it can't be moved to nvgpu_cbc.

Modified code to use above updated data structures.

Removed cbc init sequence from gr and added in
common cbc unit. This sequence is getting called
from common nvgpu init code.

JIRA NVGPU-2896
JIRA NVGPU-2897

Change-Id: I1a1b1e73b75396d61de684f413ebc551a1202a57
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033286
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-03-13 16:59:06 -07:00
committed by mobile promotions
parent ac10ac960f
commit a2bc7d5923
37 changed files with 259 additions and 172 deletions
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8
drivers/gpu/nvgpu/common/fb/fb_gv11b.c
View File

@@ -121,7 +121,7 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
}
}
void gv11b_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u32 compbit_base_post_divide;
u64 compbit_base_post_multiply64;
@@ -130,10 +130,10 @@ void gv11b_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
compbit_store_iova = nvgpu_mem_get_phys_addr(g,
&gr->compbit_store.mem);
&cbc->compbit_store.mem);
} else {
compbit_store_iova = nvgpu_mem_get_addr(g,
&gr->compbit_store.mem);
&cbc->compbit_store.mem);
}
/* must be aligned to 64 KB */
compbit_store_iova = roundup(compbit_store_iova, (u64)SZ_64K);
@@ -167,7 +167,7 @@ void gv11b_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
nvgpu_log(g, gpu_dbg_fn, "cbc base %x",
gk20a_readl(g, fb_mmu_cbc_base_r()));
gr->compbit_store.base_hw = compbit_base_post_divide;
cbc->compbit_store.base_hw = compbit_base_post_divide;
}

3
drivers/gpu/nvgpu/common/fb/fb_gv11b.h
View File

@@ -30,11 +30,12 @@
struct gk20a;
struct gr_gk20a;
struct nvgpu_cbc;
void gv11b_fb_init_hw(struct gk20a *g);
void gv11b_fb_init_fs_state(struct gk20a *g);
void gv11b_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr);
void gv11b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
void gv11b_fb_reset(struct gk20a *g);
void gv11b_fb_hub_isr(struct gk20a *g);

10
drivers/gpu/nvgpu/common/fb/fb_tu104.c
View File

@@ -424,7 +424,7 @@ int fb_tu104_mmu_invalidate_replay(struct gk20a *g,
return err;
}
void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc)
{
u64 base_divisor;
u64 compbit_store_base;
@@ -434,13 +434,13 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
u32 cbc_top_size;
u32 cbc_max;
compbit_store_pa = nvgpu_mem_get_addr(g, &gr->compbit_store.mem);
compbit_store_pa = nvgpu_mem_get_addr(g, &cbc->compbit_store.mem);
base_divisor = g->ops.cbc.get_base_divisor(g);
compbit_store_base = DIV_ROUND_UP(compbit_store_pa, base_divisor);
cbc_start_addr = (u64)g->ltc_count * (compbit_store_base <<
fb_mmu_cbc_base_address_alignment_shift_v());
cbc_end_addr = cbc_start_addr + gr->compbit_backing_size;
cbc_end_addr = cbc_start_addr + cbc->compbit_backing_size;
cbc_top = (cbc_end_addr / g->ltc_count) >>
fb_mmu_cbc_base_address_alignment_shift_v();
@@ -452,7 +452,7 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
cbc_max = nvgpu_readl(g, fb_mmu_cbc_max_r());
cbc_max = set_field(cbc_max,
fb_mmu_cbc_max_comptagline_m(),
fb_mmu_cbc_max_comptagline_f(gr->max_comptag_lines));
fb_mmu_cbc_max_comptagline_f(cbc->max_comptag_lines));
nvgpu_writel(g, fb_mmu_cbc_max_r(), cbc_max);
nvgpu_writel(g, fb_mmu_cbc_base_r(),
@@ -464,7 +464,7 @@ void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr)
(u32)(compbit_store_pa & 0xffffffffU),
compbit_store_base);
gr->compbit_store.base_hw = compbit_store_base;
cbc->compbit_store.base_hw = compbit_store_base;
}

3
drivers/gpu/nvgpu/common/fb/fb_tu104.h
View File

@@ -28,6 +28,7 @@
struct gk20a;
struct gr_gk20a;
struct nvgpu_mem;
struct nvgpu_cbc;
void tu104_fb_enable_hub_intr(struct gk20a *g);
void tu104_fb_disable_hub_intr(struct gk20a *g);
@@ -55,7 +56,7 @@ int fb_tu104_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
int fb_tu104_mmu_invalidate_replay(struct gk20a *g,
u32 invalidate_replay_val);
void tu104_fb_cbc_configure(struct gk20a *g, struct gr_gk20a *gr);
void tu104_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
int tu104_fb_apply_pdb_cache_war(struct gk20a *g);
size_t tu104_fb_get_vidmem_size(struct gk20a *g);