nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 02:52:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: cbc: move cbc related code from gr

Browse Source 
Moved cbc related code and data from gr to cbc unit.

Ltc and cbc related data is moved from gr header:
1. Ltc related data moved from gr_gk20a -> gk20a and it
will be moved eventually to ltc unit:
u32 slices_per_ltc;
u32 cacheline_size;

2. cbc data moved from gr_gk20a -> nvgpu_cbc
u32 compbit_backing_size;
u32 comptags_per_cacheline;
u32 gobs_per_comptagline_per_slice;
u32 max_comptag_lines;
struct gk20a_comptag_allocator comp_tags;
struct compbit_store_desc compbit_store;

3. Following config data moved gr_gk20a -> gk20a
u32 comptag_mem_deduct;
u32 max_comptag_mem;
These are part of initial config which should be available
during nvgpu_probe. So it can't be moved to nvgpu_cbc.

Modified code to use above updated data structures.

Removed cbc init sequence from gr and added in
common cbc unit. This sequence is getting called
from common nvgpu init code.

JIRA NVGPU-2896
JIRA NVGPU-2897

Change-Id: I1a1b1e73b75396d61de684f413ebc551a1202a57
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033286
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-03-13 16:59:06 -07:00
committed by mobile promotions
parent ac10ac960f
commit a2bc7d5923
37 changed files with 259 additions and 172 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/gpu/nvgpu/hal/cbc/cbc_tu104.c
View File

@@ -1,4 +1,6 @@
/*
* TU104 CBC
*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,10 +45,10 @@ u64 tu104_cbc_get_base_divisor(struct gk20a *g)
ltc_ltcs_ltss_cbc_base_alignment_shift_v();
}
int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr)
int tu104_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc)
{
/* max memory size (MB) to cover */
u32 max_size = gr->max_comptag_mem;
u32 max_size = g->max_comptag_mem;
/* one tag line covers 64KB */
u32 max_comptag_lines = max_size << 4U;
u32 compbit_backing_size;
@@ -64,7 +66,7 @@ int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr)
}
/* Already initialized */
if (gr->max_comptag_lines != 0U) {
if (cbc->max_comptag_lines != 0U) {
return 0;
}
@@ -78,7 +80,7 @@ int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr)
ctags_size =
ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(cbc_param);
ctags_per_cacheline = gr->cacheline_size / ctags_size;
ctags_per_cacheline = g->cacheline_size / ctags_size;
amap_divide_rounding = (U32(2U) * U32(1024U)) <<
ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(cbc_param);
@@ -86,9 +88,9 @@ int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr)
ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(cbc_param);
compbit_backing_size =
roundup(max_comptag_lines * ctags_size, gr->cacheline_size);
roundup(max_comptag_lines * ctags_size, g->cacheline_size);
compbit_backing_size =
compbit_backing_size * gr->slices_per_ltc * g->ltc_count;
compbit_backing_size * g->slices_per_ltc * g->ltc_count;
compbit_backing_size += g->ltc_count * amap_divide_rounding;
compbit_backing_size += amap_swizzle_rounding;
@@ -102,22 +104,22 @@ int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr)
return err;
}
err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines);
err = gk20a_comptag_allocator_init(g, &cbc->comp_tags, max_comptag_lines);
if (err != 0) {
return err;
}
gr->max_comptag_lines = max_comptag_lines;
gr->comptags_per_cacheline = ctags_per_cacheline;
gr->gobs_per_comptagline_per_slice = ctags_size;
gr->compbit_backing_size = compbit_backing_size;
cbc->max_comptag_lines = max_comptag_lines;
cbc->comptags_per_cacheline = ctags_per_cacheline;
cbc->gobs_per_comptagline_per_slice = ctags_size;
cbc->compbit_backing_size = compbit_backing_size;
nvgpu_log_info(g, "compbit backing store size : %d",
compbit_backing_size);
nvgpu_log_info(g, "max comptag lines : %d",
max_comptag_lines);
nvgpu_log_info(g, "gobs_per_comptagline_per_slice: %d",
gr->gobs_per_comptagline_per_slice);
cbc->gobs_per_comptagline_per_slice);
return 0;
}
@@ -125,11 +127,10 @@ int tu104_cbc_alloc_comptags(struct gk20a *g, struct gr_gk20a *gr)
int tu104_cbc_ctrl(struct gk20a *g, enum nvgpu_cbc_op op,
u32 min, u32 max)
{
struct gr_gk20a *gr = &g->gr;
struct nvgpu_timeout timeout;
int err = 0;
u32 ltc, slice, ctrl1, val, hw_op = 0U;
u32 slices_per_ltc = gr->slices_per_ltc;
u32 slices_per_ltc = g->slices_per_ltc;
u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
const u32 max_lines = 16384U;
@@ -138,7 +139,7 @@ int tu104_cbc_ctrl(struct gk20a *g, enum nvgpu_cbc_op op,
trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max);
if (gr->compbit_store.mem.size == 0U) {
if (g->cbc->compbit_store.mem.size == 0U) {
return 0;
}
@@ -218,11 +219,9 @@ out:
return err;
}
void tu104_cbc_init(struct gk20a *g, struct gr_gk20a *gr)
void tu104_cbc_init(struct gk20a *g, struct nvgpu_cbc *cbc)
{
g->ops.fb.cbc_configure(g, gr);
g->ops.fb.cbc_configure(g, cbc);
g->ops.cbc.ctrl(g, nvgpu_cbc_op_invalidate,
0, gr->max_comptag_lines - 1U);
0, cbc->max_comptag_lines - 1U);
}