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gpu: nvgpu: cbc: move cbc related code from gr

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Moved cbc related code and data from gr to cbc unit.

Ltc and cbc related data is moved from gr header:
1. Ltc related data moved from gr_gk20a -> gk20a and it
will be moved eventually to ltc unit:
u32 slices_per_ltc;
u32 cacheline_size;

2. cbc data moved from gr_gk20a -> nvgpu_cbc
u32 compbit_backing_size;
u32 comptags_per_cacheline;
u32 gobs_per_comptagline_per_slice;
u32 max_comptag_lines;
struct gk20a_comptag_allocator comp_tags;
struct compbit_store_desc compbit_store;

3. Following config data moved gr_gk20a -> gk20a
u32 comptag_mem_deduct;
u32 max_comptag_mem;
These are part of initial config which should be available
during nvgpu_probe. So it can't be moved to nvgpu_cbc.

Modified code to use above updated data structures.

Removed cbc init sequence from gr and added in
common cbc unit. This sequence is getting called
from common nvgpu init code.

JIRA NVGPU-2896
JIRA NVGPU-2897

Change-Id: I1a1b1e73b75396d61de684f413ebc551a1202a57
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033286
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-03-13 16:59:06 -07:00
committed by mobile promotions
parent ac10ac960f
commit a2bc7d5923
37 changed files with 259 additions and 172 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/nvgpu/os/linux/cde.c
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@@ -29,6 +29,7 @@
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/kmem.h>
#include <nvgpu/log.h>
#include <nvgpu/cbc.h>
#include <nvgpu/bug.h>
#include <nvgpu/firmware.h>
#include <nvgpu/os_sched.h>
@@ -102,12 +103,13 @@ __must_hold(&cde_app->mutex)
struct gk20a *g = &l->g;
struct channel_gk20a *ch = cde_ctx->ch;
struct vm_gk20a *vm = ch->vm;
struct nvgpu_cbc *cbc = g->cbc;
trace_gk20a_cde_remove_ctx(cde_ctx);
/* release mapped memory */
gk20a_deinit_cde_img(cde_ctx);
nvgpu_gmmu_unmap(vm, &g->gr.compbit_store.mem,
nvgpu_gmmu_unmap(vm, &cbc->compbit_store.mem,
cde_ctx->backing_store_vaddr);
/*
@@ -403,6 +405,7 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
{
struct nvgpu_os_linux *l = cde_ctx->l;
struct gk20a *g = &l->g;
struct nvgpu_cbc *cbc = g->cbc;
struct nvgpu_mem *target_mem;
u32 *target_mem_ptr;
u64 new_data;
@@ -417,11 +420,11 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
switch (param->id) {
case TYPE_PARAM_COMPTAGS_PER_CACHELINE:
new_data = g->gr.comptags_per_cacheline;
new_data = cbc->comptags_per_cacheline;
break;
case TYPE_PARAM_GPU_CONFIGURATION:
new_data = (u64)g->ltc_count * g->gr.slices_per_ltc *
g->gr.cacheline_size;
new_data = (u64)g->ltc_count * g->slices_per_ltc *
g->cacheline_size;
break;
case TYPE_PARAM_FIRSTPAGEOFFSET:
new_data = cde_ctx->surf_param_offset;
@@ -439,7 +442,7 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
new_data = cde_ctx->compbit_size;
break;
case TYPE_PARAM_BACKINGSTORE_SIZE:
new_data = g->gr.compbit_store.mem.size;
new_data = cbc->compbit_store.mem.size;
break;
case TYPE_PARAM_SOURCE_SMMU_ADDR:
new_data = gpuva_to_iova_base(cde_ctx->vm,
@@ -451,10 +454,10 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
}
break;
case TYPE_PARAM_BACKINGSTORE_BASE_HW:
new_data = g->gr.compbit_store.base_hw;
new_data = cbc->compbit_store.base_hw;
break;
case TYPE_PARAM_GOBS_PER_COMPTAGLINE_PER_SLICE:
new_data = g->gr.gobs_per_comptagline_per_slice;
new_data = cbc->gobs_per_comptagline_per_slice;
break;
case TYPE_PARAM_SCATTERBUFFER:
new_data = cde_ctx->scatterbuffer_vaddr;
@@ -1014,6 +1017,7 @@ __releases(&l->cde_app->mutex)
{
struct gk20a *g = &l->g;
struct gk20a_cde_ctx *cde_ctx = NULL;
struct nvgpu_cbc *cbc = g->cbc;
struct gk20a_comptags comptags;
struct nvgpu_os_buffer os_buf = {
compbits_scatter_buf,
@@ -1199,7 +1203,7 @@ __releases(&l->cde_app->mutex)
}
nvgpu_log(g, gpu_dbg_cde, "cde: buffer=cbc, size=%zu, gpuva=%llx\n",
g->gr.compbit_store.mem.size, cde_ctx->backing_store_vaddr);
cbc->compbit_store.mem.size, cde_ctx->backing_store_vaddr);
nvgpu_log(g, gpu_dbg_cde, "cde: buffer=compbits, size=%llu, gpuva=%llx\n",
cde_ctx->compbit_size, cde_ctx->compbit_vaddr);
nvgpu_log(g, gpu_dbg_cde, "cde: buffer=scatterbuffer, size=%llu, gpuva=%llx\n",
@@ -1310,10 +1314,10 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
{
struct nvgpu_os_linux *l = cde_ctx->l;
struct gk20a *g = &l->g;
struct nvgpu_cbc *cbc = g->cbc;
struct nvgpu_firmware *img;
struct channel_gk20a *ch;
struct tsg_gk20a *tsg;
struct gr_gk20a *gr = &g->gr;
struct nvgpu_setup_bind_args setup_bind_args;
int err = 0;
u64 vaddr;
@@ -1366,12 +1370,12 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
}
/* map backing store to gpu virtual space */
vaddr = nvgpu_gmmu_map(ch->vm, &gr->compbit_store.mem,
g->gr.compbit_store.mem.size,
vaddr = nvgpu_gmmu_map(ch->vm, &cbc->compbit_store.mem,
cbc->compbit_store.mem.size,
NVGPU_VM_MAP_CACHEABLE,
gk20a_mem_flag_read_only,
false,
gr->compbit_store.mem.aperture);
cbc->compbit_store.mem.aperture);
if (!vaddr) {
nvgpu_warn(g, "cde: cannot map compression bit backing store");
@@ -1398,7 +1402,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
return 0;
err_init_cde_img:
nvgpu_gmmu_unmap(ch->vm, &g->gr.compbit_store.mem, vaddr);
nvgpu_gmmu_unmap(ch->vm, &cbc->compbit_store.mem, vaddr);
err_map_backingstore:
err_setup_bind:
nvgpu_vm_put(ch->vm);