From a3068cebc68bf9288768c662da987528e6df8d60 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 24 Jan 2019 18:11:02 +0530 Subject: [PATCH] gpu: nvgpu: patch SMPC only for main context image In __gr_gk20a_exec_ctx_ops(), we right now call gr_gk20a_ctx_patch_smpc() even if operations are on pm_ctx image which is incorrect since this is only required for SMPC operations on main context image Fix this by not calling gr_gk20a_ctx_patch_smpc() for pm_ctx image Jira NVGPU-1527 Jira NVGPU-1613 Change-Id: I5111fb0e6ea1f329750b42a37a98f5c006b47deb Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2011095 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6c2c5191d..3fd9a8339 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -5601,7 +5601,6 @@ void gk20a_gr_init_ovr_sm_dsm_perf(void) static int gr_gk20a_ctx_patch_smpc(struct gk20a *g, struct channel_gk20a *ch, u32 addr, u32 data, - struct nvgpu_mem *mem, struct nvgpu_gr_ctx *gr_ctx) { u32 num_gpc = nvgpu_gr_config_get_gpc_count(g->gr.config); @@ -7018,11 +7017,13 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, offsets[j] + 4U, v); } - /* check to see if we need to add a special WAR - for some of the SMPC perf regs */ - gr_gk20a_ctx_patch_smpc(g, ch, offset_addrs[j], - v, current_mem, gr_ctx); - + if (current_mem == &gr_ctx->mem) { + /* check to see if we need to add a special WAR + for some of the SMPC perf regs */ + gr_gk20a_ctx_patch_smpc(g, ch, + offset_addrs[j], + v, gr_ctx); + } } else { /* read pass */ ctx_ops[i].value_lo = nvgpu_mem_rd(g, current_mem, offsets[0]);