From a321679a5d1333372e718eb739c5d15b2616a380 Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Fri, 12 May 2023 06:28:38 +0000 Subject: [PATCH] gpu: nvgpu: add is_gsp_supported flag This patch adds is_gsp_supported flag and initializes it for GA10B, TU104. Further, this flag is checked before initializaing GSP LITE falcon. JIRA NVGPU-9983 Change-Id: If0a4a3095c15cac113895f3d114e731f35211c5d Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2902651 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Lakshmanan M Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 14 +++++++++----- drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h | 3 ++- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 2f357bcd2..b7231d146 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -273,10 +273,12 @@ static int nvgpu_falcons_sw_init(struct gk20a *g) } #endif - err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_GSPLITE); - if (err != 0) { - nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE"); - goto done_nvenc; + if (g->ops.gsp.is_gsp_supported != false) { + err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_GSPLITE); + if (err != 0) { + nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE"); + goto done_nvenc; + } } return 0; @@ -308,7 +310,9 @@ static void nvgpu_falcons_sw_free(struct gk20a *g) g->ops.falcon.falcon_sw_free(g, FALCON_ID_FECS); #ifdef CONFIG_NVGPU_DGPU - g->ops.falcon.falcon_sw_free(g, FALCON_ID_GSPLITE); + if (g->ops.gsp.is_gsp_supported != false) { + g->ops.falcon.falcon_sw_free(g, FALCON_ID_GSPLITE); + } g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVDEC); g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVENC); g->ops.falcon.falcon_sw_free(g, FALCON_ID_SEC2); diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 46033a27e..63c009230 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1353,6 +1353,7 @@ static const struct gops_therm ga10b_ops_therm = { }; static const struct gops_gsp ga10b_ops_gsp = { + .is_gsp_supported = true, .falcon_base_addr = ga10b_gsp_falcon_base_addr, .falcon2_base_addr = ga10b_gsp_falcon2_base_addr, .gsp_reset = ga10b_gsp_engine_reset, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index a0c6a2545..b8eb836a6 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1692,6 +1692,7 @@ static const struct gops_sec2 tu104_ops_sec2 = { #ifdef CONFIG_NVGPU_LS_PMU static const struct gops_gsp tu104_ops_gsp = { + .is_gsp_supported = true, .falcon_base_addr = tu104_gsp_falcon_base_addr, .falcon_setup_boot_config = tu104_gsp_flcn_setup_boot_config, .gsp_reset = tu104_gsp_reset, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h index b513208bf..4ce46b987 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,6 +36,7 @@ struct gops_gsp { int (*gsp_reset)(struct gk20a *g); bool (*validate_mem_integrity)(struct gk20a *g); bool (*is_debug_mode_enabled)(struct gk20a *g); + bool is_gsp_supported; #ifdef CONFIG_NVGPU_GSP_SCHEDULER u32 (*gsp_get_queue_head)(u32 i); u32 (*gsp_get_queue_head_size)(void);