gpu: nvgpu: disable golden context image verification

- Disable golden context image verification until ctxsw fw for orin
safety is ready for this feature.
- Make NULL check for hal set_default_compute_regs else it causes crash
for orin safety.

Bug 3456240

Change-Id: I1f6ca9d78f22cc6776bb0b3a9e05f22171095c7f
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645666
(cherry picked from commit 3907d1b315e1247243632fefdcbce69d58090681)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2644533
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Shashank Singh
2021-12-20 05:34:31 +00:00
committed by mobile promotions
parent 4e227b3e80
commit a372ec9a38
5 changed files with 5 additions and 5 deletions

View File

@@ -76,7 +76,6 @@ ifeq ($(profile),$(filter $(profile),safety_debug safety_release))
# Enable golden context verification only for safety debug/release build # Enable golden context verification only for safety debug/release build
NVGPU_COMMON_CFLAGS += \ NVGPU_COMMON_CFLAGS += \
-DCONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION \
-DCONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY -DCONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY
## For tesing of CTXSW FW error codes manually, enable below configs in safety build. ## For tesing of CTXSW FW error codes manually, enable below configs in safety build.

View File

@@ -881,7 +881,9 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
subctx); subctx);
#ifndef CONFIG_NVGPU_NON_FUSA #ifndef CONFIG_NVGPU_NON_FUSA
if (g->ops.gr.init.set_default_compute_regs != NULL) {
g->ops.gr.init.set_default_compute_regs(g, gr_ctx); g->ops.gr.init.set_default_compute_regs(g, gr_ctx);
}
#endif #endif
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, "done"); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, "done");

View File

@@ -477,7 +477,6 @@ nvgpu_gr_global_ctx_buffer_get_mem
nvgpu_gr_global_ctx_buffer_map nvgpu_gr_global_ctx_buffer_map
nvgpu_gr_global_ctx_buffer_ready nvgpu_gr_global_ctx_buffer_ready
nvgpu_gr_global_ctx_buffer_unmap nvgpu_gr_global_ctx_buffer_unmap
nvgpu_gr_global_ctx_compare_golden_images
nvgpu_gr_global_ctx_deinit_local_golden_image nvgpu_gr_global_ctx_deinit_local_golden_image
nvgpu_gr_global_ctx_desc_alloc nvgpu_gr_global_ctx_desc_alloc
nvgpu_gr_global_ctx_desc_free nvgpu_gr_global_ctx_desc_free

View File

@@ -493,7 +493,6 @@ nvgpu_gr_global_ctx_buffer_get_mem
nvgpu_gr_global_ctx_buffer_map nvgpu_gr_global_ctx_buffer_map
nvgpu_gr_global_ctx_buffer_ready nvgpu_gr_global_ctx_buffer_ready
nvgpu_gr_global_ctx_buffer_unmap nvgpu_gr_global_ctx_buffer_unmap
nvgpu_gr_global_ctx_compare_golden_images
nvgpu_gr_global_ctx_deinit_local_golden_image nvgpu_gr_global_ctx_deinit_local_golden_image
nvgpu_gr_global_ctx_desc_alloc nvgpu_gr_global_ctx_desc_alloc
nvgpu_gr_global_ctx_desc_free nvgpu_gr_global_ctx_desc_free

View File

@@ -725,12 +725,13 @@ int test_gr_setup_alloc_obj_ctx(struct unit_module *m,
if (err != 0) { if (err != 0) {
unit_return_fail(m, "local golden image alloc failed\n"); unit_return_fail(m, "local golden image alloc failed\n");
} }
#if 0
err = nvgpu_gr_global_ctx_alloc_local_golden_image(g, err = nvgpu_gr_global_ctx_alloc_local_golden_image(g,
&g->gr->golden_image->local_golden_image_copy, 0x800); &g->gr->golden_image->local_golden_image_copy, 0x800);
if (err != 0) { if (err != 0) {
unit_return_fail(m, "local golden image copy alloc failed\n"); unit_return_fail(m, "local golden image copy alloc failed\n");
} }
#endif
/* Test with channel and tsg */ /* Test with channel and tsg */
err = gr_test_setup_allocate_ch_tsg(m, g); err = gr_test_setup_allocate_ch_tsg(m, g);
if (err != 0) { if (err != 0) {