diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
index 7b9f51def..b2f140723 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
@@ -281,14 +281,14 @@ int boardobjgrp_pmuinithandle_impl(struct gk20a *g,
 
 	status = boardobjgrp_pmucmd_pmuinithandle_impl(g, pboardobjgrp,
 		&pboardobjgrp->pmu.set);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "failed to init pmu set cmd");
 		goto boardobjgrp_pmuinithandle_exit;
 	}
 
 	status = boardobjgrp_pmucmd_pmuinithandle_impl(g, pboardobjgrp,
 		&pboardobjgrp->pmu.getstatus);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "failed to init get status command");
 		goto boardobjgrp_pmuinithandle_exit;
 	}
@@ -302,7 +302,7 @@ int boardobjgrp_pmuinithandle_impl(struct gk20a *g,
 
 	/* Send the BOARDOBJGRP to the pmu via RM_PMU_BOARDOBJ_CMD_GRP. */
 	status = pboardobjgrp->pmuset(g, pboardobjgrp);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "failed to send boardobg grp to PMU");
 	}
 
@@ -382,14 +382,14 @@ int boardobjgrp_pmudatainit_legacy(struct gk20a *g,
 		status = pboardobjgrp->pmudatainstget(g,
 				(struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
 				&ppmudata, index);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g, "could not get object instance");
 			goto boardobjgrppmudatainit_legacy_done;
 		}
 
 		/* Initialize the PMU Data */
 		status = pboardobj->pmudatainit(g, pboardobj, ppmudata);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"could not parse pmu for device %d", index);
 			goto boardobjgrppmudatainit_legacy_done;
@@ -422,7 +422,7 @@ int boardobjgrp_pmudatainit_super(struct gk20a *g, struct boardobjgrp
 	/* Initialize the PMU HDR data.*/
 	status = pboardobjgrp->pmuhdrdatainit(g, pboardobjgrp, pboardobjgrppmu,
 							pboardobjgrp->mask);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "unable to init boardobjgrp pmuhdr data");
 		goto boardobjgrppmudatainit_super_done;
 	}
@@ -431,14 +431,14 @@ int boardobjgrp_pmudatainit_super(struct gk20a *g, struct boardobjgrp
 		status = pboardobjgrp->pmudatainstget(g,
 				(struct nv_pmu_boardobjgrp *)pboardobjgrppmu,
 				&ppmudata, index);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g, "could not get object instance");
 			goto boardobjgrppmudatainit_super_done;
 		}
 
 		/* Initialize the PMU Data and send to PMU */
 		status = pboardobj->pmudatainit(g, pboardobj, ppmudata);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"could not parse pmu for device %d", index);
 			goto boardobjgrppmudatainit_super_done;
@@ -503,7 +503,7 @@ int boardobjgrp_pmuset_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp)
 	memset(pcmd->buf, 0x0, pcmd->fbsize);
 	status = pboardobjgrp->pmudatainit(g, pboardobjgrp,
 			pcmd->buf);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not parse pmu data");
 		goto boardobjgrp_pmuset_exit;
 	}
@@ -527,7 +527,7 @@ int boardobjgrp_pmuset_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp)
 	/* Send the SET PMU CMD to the PMU */
 	status = boardobjgrp_pmucmdsend(g, pboardobjgrp,
 			pcmd);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not send SET CMD to PMU");
 		goto boardobjgrp_pmuset_exit;
 	}
@@ -562,7 +562,7 @@ int boardobjgrp_pmuset_impl_v1(struct gk20a *g,
 	memset(pcmd->buf, 0x0, pcmd->fbsize);
 	status = pboardobjgrp->pmudatainit(g, pboardobjgrp,
 			pcmd->buf);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not parse pmu data");
 		goto boardobjgrp_pmuset_exit;
 	}
@@ -584,7 +584,7 @@ int boardobjgrp_pmuset_impl_v1(struct gk20a *g,
 	/* Send the SET PMU CMD to the PMU using RPC*/
 	status = boardobjgrp_pmucmdsend_rpc(g, pboardobjgrp,
 			pcmd, false);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not send SET CMD to PMU");
 		goto boardobjgrp_pmuset_exit;
 	}
@@ -646,7 +646,7 @@ boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp,
 	memset(pcmd->buf, 0x0, pcmd->fbsize);
 	status = pboardobjgrp->pmuhdrdatainit(g, pboardobjgrp,
 					pcmd->buf, mask);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not init PMU HDR data");
 		goto boardobjgrp_pmugetstatus_exit;
 	}
@@ -655,7 +655,7 @@ boardobjgrp_pmugetstatus_impl(struct gk20a *g, struct boardobjgrp *pboardobjgrp,
 	/* Send the GET_STATUS PMU CMD to the PMU */
 	status = boardobjgrp_pmucmdsend(g, pboardobjgrp,
 				&pboardobjgrp->pmu.getstatus);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not send GET_STATUS cmd to PMU");
 		goto boardobjgrp_pmugetstatus_exit;
 	}
@@ -703,7 +703,7 @@ boardobjgrp_pmugetstatus_impl_v1(struct gk20a *g, struct boardobjgrp *pboardobjg
 	memset(pcmd->buf, 0x0, pcmd->fbsize);
 	status = pboardobjgrp->pmuhdrdatainit(g, pboardobjgrp,
 			pcmd->buf, mask);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not init PMU HDR data");
 		goto boardobjgrp_pmugetstatus_exit;
 	}
@@ -717,7 +717,7 @@ boardobjgrp_pmugetstatus_impl_v1(struct gk20a *g, struct boardobjgrp *pboardobjg
 	/* Send the GET_STATUS PMU CMD to the PMU */
 	status = boardobjgrp_pmucmdsend_rpc(g, pboardobjgrp,
 			pcmd, true);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "could not send GET_STATUS cmd to PMU");
 		goto boardobjgrp_pmugetstatus_exit;
 	}
@@ -992,7 +992,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
 				boardobjgrp_pmucmdhandler,
 				(void *)&handlerparams,
 				&seqdesc, ~0);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"unable to post boardobj grp cmd for unit %x cmd id %x",
 			cmd.hdr.unit_id, pcmd->id);
@@ -1038,7 +1038,7 @@ static int boardobjgrp_pmucmdsend_rpc(struct gk20a *g,
 		pcmd->dmem_buffer_size,
 		NULL, NULL, copy_out);
 
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "Failed to execute RPC, status=0x%x", status);
 	}
 
diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e255.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e255.c
index 42c655703..8a6f46406 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e255.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e255.c
@@ -38,7 +38,7 @@ int boardobjgrpconstruct_e255(struct gk20a *g,
 
 	objslots = 255;
 	status = boardobjgrpmask_e255_init(&pboardobjgrp_e255->mask, NULL);
-	if (status) {
+	if (status != 0) {
 		goto boardobjgrpconstruct_e255_exit;
 	}
 
@@ -48,7 +48,7 @@ int boardobjgrpconstruct_e255(struct gk20a *g,
 	pboardobjgrp_e255->super.mask     = &(pboardobjgrp_e255->mask.super);
 
 	status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super);
-	if (status) {
+	if (status != 0) {
 		goto boardobjgrpconstruct_e255_exit;
 	}
 
@@ -81,7 +81,7 @@ int boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g,
 	status = boardobjgrpmask_export(mask,
 				mask->bitcount,
 				&pgrpe255->obj_mask.super);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "e255 init:failed export grpmask");
 		return status;
 	}
diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e32.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e32.c
index ce8f13320..6dfbf333f 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e32.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp_e32.c
@@ -28,7 +28,7 @@
 #include "ctrl/ctrlboardobj.h"
 
 
-int  boardobjgrpconstruct_e32(struct gk20a *g,
+int boardobjgrpconstruct_e32(struct gk20a *g,
 			      struct boardobjgrp_e32 *pboardobjgrp_e32)
 {
 	int status;
@@ -38,7 +38,7 @@ int  boardobjgrpconstruct_e32(struct gk20a *g,
 	objslots = 32;
 
 	status = boardobjgrpmask_e32_init(&pboardobjgrp_e32->mask, NULL);
-	if (status) {
+	if (status != 0) {
 		goto boardobjgrpconstruct_e32_exit;
 	}
 
@@ -48,7 +48,7 @@ int  boardobjgrpconstruct_e32(struct gk20a *g,
 	pboardobjgrp_e32->super.mask     = &(pboardobjgrp_e32->mask.super);
 
 	status = boardobjgrp_construct_super(g, &pboardobjgrp_e32->super);
-	if (status) {
+	if (status != 0) {
 		goto boardobjgrpconstruct_e32_exit;
 	}
 
@@ -79,7 +79,7 @@ int boardobjgrp_pmuhdrdatainit_e32(struct gk20a *g,
 	status = boardobjgrpmask_export(mask,
 				mask->bitcount,
 				&pgrpe32->obj_mask.super);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "e32 init:failed export grpmask");
 		return status;
 	}
diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
index 1c24550ff..d1af194b5 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
@@ -30,7 +30,7 @@
 #define BOARDOBJGRPMASK_NORMALIZE(_pmask)                                      \
 	((_pmask)->data[(_pmask)->maskdatacount-1U] &= (_pmask)->lastmaskfilter)
 
-u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
+int boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
 		struct ctrl_boardobjgrp_mask *extmask)
 {
 	if (mask == NULL) {
@@ -54,7 +54,7 @@ u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
 		boardobjgrpmask_import(mask, bitsize, extmask);
 }
 
-u32 boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
+int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
 		struct ctrl_boardobjgrp_mask *extmask)
 {
 	u8 index;
@@ -100,7 +100,7 @@ u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize,
 	return 0;
 }
 
-u32 boardobjgrpmask_clr(struct boardobjgrpmask *mask)
+int boardobjgrpmask_clr(struct boardobjgrpmask *mask)
 {
 	u8 index;
 
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c
index c5f8e1c6c..942d48195 100644
--- a/drivers/gpu/nvgpu/common/falcon/falcon.c
+++ b/drivers/gpu/nvgpu/common/falcon/falcon.c
@@ -303,7 +303,7 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src,
 	u32 total_block_read = 0;
 	u32 byte_read_count = 0;
 	u32 i = 0;
-	u32 status = 0;
+	int status = 0;
 
 	nvgpu_info(flcn->g, " offset 0x%x  size %d bytes", src, size);
 
@@ -324,7 +324,7 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src,
 				(u8 *)buff, byte_read_count, 0);
 		}
 
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(flcn->g, "MEM print failed");
 			break;
 		}
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp106.c b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
index b14906137..5fadc91bc 100644
--- a/drivers/gpu/nvgpu/common/therm/therm_gp106.c
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.c
@@ -99,9 +99,9 @@ int gp106_elcg_init_idle_filters(struct gk20a *g)
 	return 0;
 }
 
-u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp)
+int gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp)
 {
-	u32 err = 0;
+	int err = 0;
 
 	if (g->curr_warn_temp != curr_warn_temp) {
 		g->curr_warn_temp = curr_warn_temp;
diff --git a/drivers/gpu/nvgpu/common/therm/therm_gp106.h b/drivers/gpu/nvgpu/common/therm/therm_gp106.h
index e29c993f5..682954742 100644
--- a/drivers/gpu/nvgpu/common/therm/therm_gp106.h
+++ b/drivers/gpu/nvgpu/common/therm/therm_gp106.h
@@ -32,6 +32,6 @@ struct gk20a;
 void gp106_get_internal_sensor_limits(s32 *max_24_8, s32 *min_24_8);
 int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8);
 int gp106_elcg_init_idle_filters(struct gk20a *g);
-u32 gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp);
+int gp106_configure_therm_alert(struct gk20a *g, s32 curr_warn_temp);
 
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h
index 803025bfe..52819e544 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h
@@ -68,15 +68,15 @@ struct boardobjgrpmask_e255 {
 };
 
 /* Init and I/O operations.*/
-u32 boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
+int boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
 		struct ctrl_boardobjgrp_mask *extmask);
-u32 boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
+int boardobjgrpmask_import(struct boardobjgrpmask *mask, u8 bitsize,
 		struct ctrl_boardobjgrp_mask *extmask);
 u32 boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize,
 		struct ctrl_boardobjgrp_mask *extmask);
 
 /* Operations on all bits of a single mask.*/
-u32 boardobjgrpmask_clr(struct boardobjgrpmask *mask);
+int boardobjgrpmask_clr(struct boardobjgrpmask *mask);
 u32 boardobjgrpmask_set(struct boardobjgrpmask *mask);
 u32 boardobjgrpmask_inv(struct boardobjgrpmask *mask);
 bool boardobjgrpmask_iszero(struct boardobjgrpmask *mask);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 47cf89982..40a98d3fc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -889,11 +889,11 @@ struct gpu_ops {
 				struct boardobjgrp_pmu_cmd *cmd);
 		} boardobj;
 		struct {
-			u32 (*volt_set_voltage)(struct gk20a *g,
+			int (*volt_set_voltage)(struct gk20a *g,
 				u32 logic_voltage_uv, u32 sram_voltage_uv);
-			u32 (*volt_get_voltage)(struct gk20a *g,
+			int (*volt_get_voltage)(struct gk20a *g,
 				u8 volt_domain, u32 *pvoltage_uv);
-			u32 (*volt_send_load_cmd_to_pmu)(struct gk20a *g);
+			int (*volt_send_load_cmd_to_pmu)(struct gk20a *g);
 		} volt;
 		struct {
 			u32 (*get_vbios_clk_domain)(u32 vbios_domain);
@@ -1022,7 +1022,7 @@ struct gpu_ops {
 		int (*get_internal_sensor_curr_temp)(struct gk20a *g, u32 *temp_f24_8);
 		void (*get_internal_sensor_limits)(s32 *max_24_8,
 							s32 *min_24_8);
-		u32 (*configure_therm_alert)(struct gk20a *g, s32 curr_warn_temp);
+		int (*configure_therm_alert)(struct gk20a *g, s32 curr_warn_temp);
 	} therm;
 	struct {
 		bool (*is_pmu_supported)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/therm/thrm.c b/drivers/gpu/nvgpu/therm/thrm.c
index c4e273184..bdcb28830 100644
--- a/drivers/gpu/nvgpu/therm/thrm.c
+++ b/drivers/gpu/nvgpu/therm/thrm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,12 +25,12 @@
 #include "thrm.h"
 #include "thrmpmu.h"
 
-u32 therm_domain_sw_setup(struct gk20a *g)
+int therm_domain_sw_setup(struct gk20a *g)
 {
-	u32 status;
+	int status;
 
 	status = therm_device_sw_setup(g);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for therm devices, status - 0x%x",
 			status);
@@ -38,7 +38,7 @@ u32 therm_domain_sw_setup(struct gk20a *g)
 	}
 
 	status = therm_channel_sw_setup(g);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for therm channel, status - 0x%x",
 			status);
diff --git a/drivers/gpu/nvgpu/therm/thrm.h b/drivers/gpu/nvgpu/therm/thrm.h
index d9d73b7fc..0d6596633 100644
--- a/drivers/gpu/nvgpu/therm/thrm.h
+++ b/drivers/gpu/nvgpu/therm/thrm.h
@@ -32,7 +32,7 @@ struct therm_pmupstate {
 	struct therm_channels therm_channelobjs;
 };
 
-u32 therm_domain_sw_setup(struct gk20a *g);
+int therm_domain_sw_setup(struct gk20a *g);
 u32 therm_domain_pmu_setup(struct gk20a *g);
 
 #endif /* NVGPU_THERM_THRM_H */
diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c
index 80ffb06b8..f22105022 100644
--- a/drivers/gpu/nvgpu/therm/thrmchannel.c
+++ b/drivers/gpu/nvgpu/therm/thrmchannel.c
@@ -40,7 +40,7 @@ static int _therm_channel_pmudatainit_device(struct gk20a *g,
 	struct nv_pmu_therm_therm_channel_device_boardobj_set *pset;
 
 	status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error updating pmu boardobjgrp for therm channel 0x%x",
 			status);
@@ -74,7 +74,7 @@ static struct boardobj *construct_channel_device(struct gk20a *g,
 
 	status = boardobj_construct_super(g, &board_obj_ptr,
 		pargs_size, pargs);
-	if (status) {
+	if (status != 0) {
 		return NULL;
 	}
 
@@ -198,7 +198,7 @@ static int devinit_get_therm_channel_table(struct gk20a *g,
 		status = boardobjgrp_objinsert(&pthermchannelobjs->super.super,
 				boardobj, obj_index);
 
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 			"unable to insert thermal device boardobj for %d", index);
 			status = -EINVAL;
@@ -222,7 +222,7 @@ int therm_channel_sw_setup(struct gk20a *g)
 	/* Construct the Super Class and override the Interfaces */
 	status = boardobjgrpconstruct_e32(g,
 			&g->therm_pmu.therm_channelobjs.super);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			  "error creating boardobjgrp for therm devices, status - 0x%x",
 			  status);
@@ -236,7 +236,7 @@ int therm_channel_sw_setup(struct gk20a *g)
 	pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget;
 
 	status = devinit_get_therm_channel_table(g, pthermchannelobjs);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -244,7 +244,7 @@ int therm_channel_sw_setup(struct gk20a *g)
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
 			therm, THERM, therm_channel, THERM_CHANNEL);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			  "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			  status);
diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c
index 2fa9edbd1..a3bad8a26 100644
--- a/drivers/gpu/nvgpu/therm/thrmdev.c
+++ b/drivers/gpu/nvgpu/therm/thrmdev.c
@@ -206,7 +206,7 @@ static struct boardobj *therm_device_construct(struct gk20a *g,
 		break;
 	}
 
-	if(status) {
+	if(status != 0) {
 		board_obj_ptr = NULL;
 		nvgpu_err(g,
 			"could not allocate memory for therm_device");
@@ -312,7 +312,7 @@ static int devinit_get_therm_device_table(struct gk20a *g,
 		status = boardobjgrp_objinsert(&pthermdeviceobjs->super.super,
 				boardobj, obj_index);
 
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 			"unable to insert thermal device boardobj for %d", index);
 			status = -EINVAL;
@@ -336,7 +336,7 @@ int therm_device_sw_setup(struct gk20a *g)
 	/* Construct the Super Class and override the Interfaces */
 	status = boardobjgrpconstruct_e32(g,
 			&g->therm_pmu.therm_deviceobjs.super);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			  "error creating boardobjgrp for therm devices, status - 0x%x",
 			  status);
@@ -350,7 +350,7 @@ int therm_device_sw_setup(struct gk20a *g)
 	pboardobjgrp->pmudatainstget = _therm_device_pmudata_instget;
 
 	status = devinit_get_therm_device_table(g, pthermdeviceobjs);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -358,7 +358,7 @@ int therm_device_sw_setup(struct gk20a *g)
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
 			therm, THERM, therm_device, THERM_DEVICE);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			  "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			  status);
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c
index 486db589a..aafa33c8a 100644
--- a/drivers/gpu/nvgpu/therm/thrmpmu.c
+++ b/drivers/gpu/nvgpu/therm/thrmpmu.c
@@ -59,7 +59,7 @@ int therm_send_pmgr_tables_to_pmu(struct gk20a *g)
 	if (!BOARDOBJGRP_IS_EMPTY(&g->therm_pmu.therm_deviceobjs.super.super)) {
 		pboardobjgrp = &g->therm_pmu.therm_deviceobjs.super.super;
 		status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"therm_send_pmgr_tables_to_pmu - therm_device failed %x",
 				status);
@@ -71,7 +71,7 @@ int therm_send_pmgr_tables_to_pmu(struct gk20a *g)
 			&g->therm_pmu.therm_channelobjs.super.super)) {
 		pboardobjgrp = &g->therm_pmu.therm_channelobjs.super.super;
 		status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"therm_send_pmgr_tables_to_pmu - therm_channel failed %x",
 				status);
@@ -83,12 +83,12 @@ exit:
 	return status;
 }
 
-static u32 therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
+static int therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
 		struct pmu_msg *msg, struct pmu_payload *payload,
 		u32 queue_id, pmu_callback callback, void* cb_param,
 		u32 *seq_desc, unsigned long timeout)
 {
-	u32 status;
+	int status;
 	struct therm_pmucmdhandler_params *handlerparams = NULL;
 
 	status = nvgpu_pmu_cmd_post(g, cmd, msg, payload,
@@ -97,7 +97,7 @@ static u32 therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
 				cb_param,
 				seq_desc,
 				timeout);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"unable to post therm cmd for unit %x cmd id %x size %x",
 			cmd->hdr.unit_id, cmd->cmd.therm.cmd_type, cmd->hdr.size);
@@ -122,7 +122,7 @@ exit:
 	return status;
 }
 
-static u32 therm_set_warn_temp_limit(struct gk20a *g)
+static int therm_set_warn_temp_limit(struct gk20a *g)
 {
 	u32 seqdesc = 0;
 	struct pmu_cmd cmd;
@@ -172,7 +172,7 @@ static u32 therm_set_warn_temp_limit(struct gk20a *g)
 				&seqdesc, ~0);
 }
 
-static u32 therm_enable_slct_notification_request(struct gk20a *g)
+static int therm_enable_slct_notification_request(struct gk20a *g)
 {
 	u32 seqdesc = 0;
 	struct pmu_cmd cmd = { {0} };
@@ -192,7 +192,7 @@ static u32 therm_enable_slct_notification_request(struct gk20a *g)
 				&seqdesc, ~0);
 }
 
-static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g)
+static int therm_send_slct_configuration_to_pmu(struct gk20a *g)
 {
 	u32 seqdesc = 0;
 	struct pmu_cmd cmd;
@@ -241,12 +241,12 @@ static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g)
 				&seqdesc, ~0);
 }
 
-u32 therm_configure_therm_alert(struct gk20a *g)
+int therm_configure_therm_alert(struct gk20a *g)
 {
-	u32 status;
+	int status;
 
 	status = therm_enable_slct_notification_request(g);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"therm_enable_slct_notification_request-failed %d",
 			status);
@@ -254,7 +254,7 @@ u32 therm_configure_therm_alert(struct gk20a *g)
 	}
 
 	status = therm_send_slct_configuration_to_pmu(g);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"therm_send_slct_configuration_to_pmu-failed %d",
 			status);
@@ -262,7 +262,7 @@ u32 therm_configure_therm_alert(struct gk20a *g)
 	}
 
 	status = therm_set_warn_temp_limit(g);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"therm_set_warn_temp_limit-failed %d",
 			status);
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.h b/drivers/gpu/nvgpu/therm/thrmpmu.h
index 42d5caaed..8081d8993 100644
--- a/drivers/gpu/nvgpu/therm/thrmpmu.h
+++ b/drivers/gpu/nvgpu/therm/thrmpmu.h
@@ -26,6 +26,6 @@
 
 int therm_send_pmgr_tables_to_pmu(struct gk20a *g);
 
-u32 therm_configure_therm_alert(struct gk20a *g);
+int therm_configure_therm_alert(struct gk20a *g);
 
 #endif /* NVGPU_THERM_THRMPMU_H */
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c
index c8f763a9d..7564b6f35 100644
--- a/drivers/gpu/nvgpu/volt/volt_dev.c
+++ b/drivers/gpu/nvgpu/volt/volt_dev.c
@@ -47,7 +47,7 @@ static int volt_device_pmu_data_init_super(struct gk20a *g,
 	struct nv_pmu_volt_volt_device_boardobj_set *pset;
 
 	status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -70,7 +70,7 @@ static int volt_device_pmu_data_init_pwm(struct gk20a *g,
 	struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset;
 
 	status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata);
-	if (status) {
+	if (status != 0) {
 		return  status;
 	}
 
@@ -93,7 +93,7 @@ static int construct_volt_device(struct gk20a *g,
 	int status = 0;
 
 	status = boardobj_construct_super(g, ppboardobj, size, pargs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -125,7 +125,7 @@ static int construct_pwm_volt_device(struct gk20a *g,
 	int status = 0;
 
 	status = construct_volt_device(g, ppboardobj, size, pargs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -191,7 +191,7 @@ static struct voltage_device *volt_volt_device_construct(struct gk20a *g,
 	if (BOARDOBJ_GET_TYPE(pargs) == CTRL_VOLT_DEVICE_TYPE_PWM) {
 		int status = construct_pwm_volt_device(g, &pboard_obj,
 				sizeof(struct voltage_device_pwm), pargs);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				" Could not allocate memory for VOLTAGE_DEVICE type (%x).",
 				BOARDOBJ_GET_TYPE(pargs));
@@ -329,7 +329,7 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g,
 	status = boardobjgrp_objinsert(
 				&p_Volt_Device_Meta_Data->volt_devices.super,
 				(struct boardobj *)pvolt_dev, entry_Idx);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"could not add VOLTAGE_DEVICE for entry %d into boardobjgrp ",
 			entry_Idx);
@@ -394,10 +394,10 @@ done:
 	return status;
 }
 
-static u32 volt_get_volt_devices_table(struct gk20a *g,
+static int volt_get_volt_devices_table(struct gk20a *g,
 		struct voltage_device_metadata *pvolt_device_metadata)
 {
-	u32 status = 0;
+	int status = 0;
 	u8 *volt_device_table_ptr = NULL;
 	struct vbios_voltage_device_table_1x_header header = { 0 };
 	struct vbios_voltage_device_table_1x_entry entry  = { 0 };
@@ -482,10 +482,10 @@ static int volt_device_volt_cmp(const void *a, const void *b)
 	return (int)a_entry->voltage_uv - (int)b_entry->voltage_uv;
 }
 
-static u32 volt_device_state_init(struct gk20a *g,
+static int volt_device_state_init(struct gk20a *g,
 			struct voltage_device *pvolt_dev)
 {
-	u32 status = 0;
+	int status = 0;
 	struct voltage_rail *pRail = NULL;
 	u8 rail_idx = 0;
 
@@ -523,7 +523,7 @@ static u32 volt_device_state_init(struct gk20a *g,
 
 		status = volt_rail_volt_dev_register(g, pRail,
 			BOARDOBJ_GET_IDX(pvolt_dev), pvolt_dev->operation_type);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"Failed to register the device with rail obj");
 			goto done;
@@ -531,7 +531,7 @@ static u32 volt_device_state_init(struct gk20a *g,
 	}
 
 done:
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "Error in building rail sw state device sw");
 	}
 
@@ -557,9 +557,9 @@ int volt_dev_pmu_setup(struct gk20a *g)
 	return status;
 }
 
-u32 volt_dev_sw_setup(struct gk20a *g)
+int volt_dev_sw_setup(struct gk20a *g)
 {
-	u32 status = 0;
+	int status = 0;
 	struct boardobjgrp *pboardobjgrp = NULL;
 	struct voltage_device *pvolt_device;
 	u8 i;
@@ -568,7 +568,7 @@ u32 volt_dev_sw_setup(struct gk20a *g)
 
 	status = boardobjgrpconstruct_e32(g,
 			&g->perf_pmu.volt.volt_dev_metadata.volt_devices);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for volt rail, status - 0x%x",
 			status);
@@ -583,7 +583,7 @@ u32 volt_dev_sw_setup(struct gk20a *g)
 	/* Obtain Voltage Rail Table from VBIOS */
 	status = volt_get_volt_devices_table(g, &g->perf_pmu.volt.
 			volt_dev_metadata);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -592,7 +592,7 @@ u32 volt_dev_sw_setup(struct gk20a *g)
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
 			volt, VOLT, volt_device, VOLT_DEVICE);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			status);
@@ -602,7 +602,7 @@ u32 volt_dev_sw_setup(struct gk20a *g)
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
 			&g->perf_pmu.volt.volt_dev_metadata.volt_devices.super,
 			volt, VOLT, volt_device, VOLT_DEVICE);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			status);
@@ -614,7 +614,7 @@ u32 volt_dev_sw_setup(struct gk20a *g)
 			       super),
 			     struct voltage_device *, pvolt_device, i) {
 		status = volt_device_state_init(g, pvolt_device);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"failure while executing devices's state init interface");
 			nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.h b/drivers/gpu/nvgpu/volt/volt_dev.h
index e36f5627d..6a5576b09 100644
--- a/drivers/gpu/nvgpu/volt/volt_dev.h
+++ b/drivers/gpu/nvgpu/volt/volt_dev.h
@@ -71,7 +71,7 @@ struct voltage_device_pwm_entry {
 };
 /* PWM end */
 
-u32 volt_dev_sw_setup(struct gk20a *g);
+int volt_dev_sw_setup(struct gk20a *g);
 int volt_dev_pmu_setup(struct gk20a *g);
 
 #endif /* NVGPU_VOLT_DEV_H */
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c
index 11367077e..f1778ee66 100644
--- a/drivers/gpu/nvgpu/volt/volt_pmu.c
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.c
@@ -60,13 +60,13 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 }
 
 
-static u32 volt_pmu_rpc_execute(struct gk20a *g,
+static int volt_pmu_rpc_execute(struct gk20a *g,
 	struct nv_pmu_volt_rpc *prpc_call)
 {
 	struct pmu_cmd cmd;
 	struct pmu_msg msg;
 	struct pmu_payload payload;
-	u32 status = 0;
+	int status = 0;
 	u32 seqdesc;
 	struct volt_rpc_pmucmdhandler_params handler;
 
@@ -98,7 +98,7 @@ static u32 volt_pmu_rpc_execute(struct gk20a *g,
 			PMU_COMMAND_QUEUE_LPQ,
 			volt_rpc_pmucmdhandler, (void *)&handler,
 			&seqdesc, ~0);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "unable to post volt RPC cmd %x",
 			cmd.cmd.volt.cmd_type);
 		goto volt_pmu_rpc_execute;
@@ -117,15 +117,15 @@ volt_pmu_rpc_execute:
 	return status;
 }
 
-u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
+int nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
 {
 	struct nv_pmu_volt_rpc rpc_call = { 0 };
-	u32 status = 0;
+	int status = 0;
 
 	rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
 
 	status =  volt_pmu_rpc_execute(g, &rpc_call);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"Error while executing LOAD RPC: status = 0x%08x.",
 			status);
@@ -134,15 +134,15 @@ u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g)
 	return status;
 }
 
-u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g)
+int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g)
 {
 	struct nvgpu_pmu *pmu = &g->pmu;
 	struct nv_pmu_rpc_struct_volt_load rpc;
-	u32 status = 0;
+	int status = 0;
 
 	memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load));
 	PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "Failed to execute RPC status=0x%x",
 			status);
 	}
@@ -150,11 +150,11 @@ u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g)
 	return status;
 }
 
-u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
+int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
 	u8 volt_domain, u32 *pvoltage_uv)
 {
 	struct nv_pmu_volt_rpc rpc_call = { 0 };
-	u32 status  = 0;
+	int status  = 0;
 	u8 rail_idx;
 
 	rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
@@ -172,7 +172,7 @@ u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
 
 	/* Execute the voltage get request via PMU RPC. */
 	status = volt_pmu_rpc_execute(g, &rpc_call);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"Error while executing volt_rail_get_voltage rpc");
 		return status;
@@ -184,12 +184,12 @@ u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
 	return status;
 }
 
-u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
+int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
 	u8 volt_domain, u32 *pvoltage_uv)
 {
 	struct nvgpu_pmu *pmu = &g->pmu;
 	struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage rpc;
-	u32 status  = 0;
+	int status  = 0;
 	u8 rail_idx;
 
 	rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
@@ -206,7 +206,7 @@ u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
 	rpc.rail_idx = rail_idx;
 
 	PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_RAIL_GET_VOLTAGE, &rpc, 0);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "Failed to execute RPC status=0x%x",
 			status);
 	}
@@ -216,12 +216,12 @@ u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
 	return status;
 }
 
-static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
+static int volt_policy_set_voltage(struct gk20a *g, u8 client_id,
 		struct ctrl_perf_volt_rail_list *prail_list)
 {
 	struct nv_pmu_volt_rpc rpc_call = { 0 };
 	struct obj_volt *pvolt = &g->perf_pmu.volt;
-	u32 status = 0;
+	int status = 0;
 	u8 policy_idx = CTRL_VOLT_POLICY_INDEX_INVALID;
 	u8 i = 0;
 
@@ -260,7 +260,7 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
 
 	/* Execute the voltage change request via PMU RPC. */
 	status = volt_pmu_rpc_execute(g, &rpc_call);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
 	}
@@ -269,7 +269,7 @@ exit:
 	return status;
 }
 
-static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
+static int volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
 		struct ctrl_volt_volt_rail_list_v1 *prail_list)
 {
 	struct nvgpu_pmu *pmu = &g->pmu;
@@ -281,7 +281,7 @@ static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
 	rpc.rail_list = *prail_list;
 
 	PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "Failed to execute RPC status=0x%x",
 			status);
 	}
@@ -289,7 +289,7 @@ static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id,
 	return status;
 }
 
-u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
+int nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
 		u32 sram_voltage_uv)
 {
 	int status = 0;
@@ -308,7 +308,7 @@ u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
 	return status;
 }
 
-u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
+int nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
 		u32 sram_voltage_uv)
 {
 	int status = 0;
@@ -328,13 +328,13 @@ u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
 	return status;
 }
 
-u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
+int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
 {
 	return g->ops.pmu_ver.volt.volt_set_voltage(g,
 		logic_voltage_uv, sram_voltage_uv);
 }
 
-u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv)
+int volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv)
 {
 	return g->ops.pmu_ver.volt.volt_get_voltage(g,
 		volt_domain, voltage_uv);
@@ -344,7 +344,7 @@ static int volt_policy_set_noiseaware_vmin(struct gk20a *g,
 		struct ctrl_volt_volt_rail_list *prail_list)
 {
 	struct nv_pmu_volt_rpc rpc_call = { 0 };
-	u32 status = 0;
+	int status = 0;
 
 	/* Set RPC parameters. */
 	rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN;
@@ -355,7 +355,7 @@ static int volt_policy_set_noiseaware_vmin(struct gk20a *g,
 
 	/* Execute the voltage change request via PMU RPC. */
 	status = volt_pmu_rpc_execute(g, &rpc_call);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
 		return -EINVAL;
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.h b/drivers/gpu/nvgpu/volt/volt_pmu.h
index c9fb8bfce..62b9a5ac7 100644
--- a/drivers/gpu/nvgpu/volt/volt_pmu.h
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.h
@@ -24,23 +24,23 @@
 #define NVGPU_VOLT_PMU_H
 
 u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g);
-u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
+int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
 		u32 sram_voltage_uv);
-u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
+int volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv);
 int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv,
 		u32 sram_voltage_uv);
 
-u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
+int nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv,
 	u32 sram_voltage_uv);
-u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
+int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
 	u8 volt_domain, u32 *pvoltage_uv);
-u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g);
+int nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g);
 
-u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
+int nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv,
 	u32 sram_voltage_uv);
-u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
+int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
 	u8 volt_domain, u32 *pvoltage_uv);
-u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g);
+int nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g);
 
 
 #endif /* NVGPU_VOLT_PMU_H */
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c
index 04fd53a38..16a5b2f9b 100644
--- a/drivers/gpu/nvgpu/volt/volt_policy.c
+++ b/drivers/gpu/nvgpu/volt/volt_policy.c
@@ -44,7 +44,7 @@ static int construct_volt_policy(struct gk20a *g,
 	int status = 0;
 
 	status = boardobj_construct_super(g, ppboardobj, size, pArgs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -64,7 +64,7 @@ static int construct_volt_policy_split_rail(struct gk20a *g,
 	int status = 0;
 
 	status = construct_volt_policy(g, ppboardobj, size, pArgs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -89,7 +89,7 @@ static int construct_volt_policy_single_rail(struct gk20a *g,
 	int status = 0;
 
 	status = construct_volt_policy(g, ppboardobj, size, pArgs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -108,7 +108,7 @@ static int volt_policy_pmu_data_init_single_rail(struct gk20a *g,
 	struct nv_pmu_volt_volt_policy_sr_boardobj_set *pset;
 
 	status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -146,7 +146,7 @@ static int volt_policy_pmu_data_init_sr_multi_step(struct gk20a *g,
 	struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *pset;
 
 	status = volt_policy_pmu_data_init_single_rail(g, pboardobj, ppmudata);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -172,7 +172,7 @@ static int volt_construct_volt_policy_single_rail_multi_step(struct gk20a *g,
 	int status = 0;
 
 	status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -200,7 +200,7 @@ static int volt_policy_pmu_data_init_split_rail(struct gk20a *g,
 	struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *pset;
 
 	status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -226,7 +226,7 @@ static int volt_construct_volt_policy_split_rail_single_step(struct gk20a *g,
 	int status = 0;
 
 	status = construct_volt_policy_split_rail(g, ppboardobj, size, pargs);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -247,7 +247,7 @@ static struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void *
 			&pboard_obj,
 			sizeof(struct voltage_policy_split_rail_single_step),
 			pargs);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"Could not allocate memory for voltage_policy");
 			pboard_obj = NULL;
@@ -258,7 +258,7 @@ static struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void *
 			&pboard_obj,
 			sizeof(struct voltage_policy_single_rail_multi_step),
 			pargs);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"Could not allocate memory for voltage_policy");
 			pboard_obj = NULL;
@@ -394,7 +394,7 @@ static int volt_get_volt_policy_table(struct gk20a *g,
 		status = boardobjgrp_objinsert(
 				&pvolt_policy_metadata->volt_policies.super,
 				(struct boardobj *)ppolicy, i);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"could not add volt_policy for entry %d into boardobjgrp ",
 				i);
@@ -457,7 +457,7 @@ static int _volt_policy_grp_pmudatainit_super(struct gk20a *g,
 	int status = 0;
 
 	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error updating pmu boardobjgrp for volt policy 0x%x",
 			 status);
@@ -499,7 +499,7 @@ int volt_policy_sw_setup(struct gk20a *g)
 
 	status = boardobjgrpconstruct_e32(g,
 			&g->perf_pmu.volt.volt_policy_metadata.volt_policies);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for volt rail, status - 0x%x",
 			status);
@@ -516,7 +516,7 @@ int volt_policy_sw_setup(struct gk20a *g)
 	/* Obtain Voltage Rail Table from VBIOS */
 	status = volt_get_volt_policy_table(g, &g->perf_pmu.volt.
 			volt_policy_metadata);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -525,7 +525,7 @@ int volt_policy_sw_setup(struct gk20a *g)
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
 			volt, VOLT, volt_policy, VOLT_POLICY);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			status);
@@ -535,7 +535,7 @@ int volt_policy_sw_setup(struct gk20a *g)
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
 		&g->perf_pmu.volt.volt_policy_metadata.volt_policies.super,
 			volt, VOLT, volt_policy, VOLT_POLICY);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			status);
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c
index b62d9a613..ab8bb4cb9 100644
--- a/drivers/gpu/nvgpu/volt/volt_rail.c
+++ b/drivers/gpu/nvgpu/volt/volt_rail.c
@@ -53,10 +53,10 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
 	return CTRL_BOARDOBJ_IDX_INVALID;
 }
 
-u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
+int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
 	*pvolt_rail, u8 volt_dev_idx, u8 operation_type)
 {
-	u32 status = 0;
+	int status = 0;
 
 	if (operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
 		if (pvolt_rail->volt_dev_idx_default ==
@@ -90,17 +90,17 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
 			volt_dev_idx);
 
 exit:
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g, "Failed to register VOLTAGE_DEVICE");
 	}
 
 	return status;
 }
 
-static u32 volt_rail_state_init(struct gk20a *g,
+static int volt_rail_state_init(struct gk20a *g,
 		struct voltage_rail *pvolt_rail)
 {
-	u32 status = 0;
+	int status = 0;
 	u32 i;
 
 	pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID;
@@ -122,7 +122,7 @@ static u32 volt_rail_state_init(struct gk20a *g,
 		NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX;
 
 	status = boardobjgrpmask_e32_init(&pvolt_rail->volt_dev_mask, NULL);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"Failed to initialize BOARDOBJGRPMASK of VOLTAGE_DEVICEs");
 	}
@@ -141,7 +141,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
-	if (status) {
+	if (status != 0) {
 		return status;
 	}
 
@@ -170,7 +170,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
 	status = boardobjgrpmask_export(&prail->volt_dev_mask.super,
 				prail->volt_dev_mask.super.bitcount,
 				&rail_pmu_data->volt_dev_mask.super);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"Failed to export BOARDOBJGRPMASK of VOLTAGE_DEVICEs");
 	}
@@ -190,7 +190,7 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
 	nvgpu_log_info(g, " ");
 	status = boardobj_construct_super(g, &board_obj_ptr,
 		sizeof(struct voltage_rail), pargs);
-	if (status) {
+	if (status != 0) {
 		return NULL;
 	}
 
@@ -424,7 +424,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 
 	status = boardobjgrpconstruct_e32(g,
 			&g->perf_pmu.volt.volt_rail_metadata.volt_rails);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for volt rail, status - 0x%x",
 			status);
@@ -442,7 +442,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 	/* Obtain Voltage Rail Table from VBIOS */
 	status = volt_get_volt_rail_table(g, &g->perf_pmu.volt.
 			volt_rail_metadata);
-	if (status) {
+	if (status != 0) {
 		goto done;
 	}
 
@@ -451,7 +451,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
 			volt, VOLT, volt_rail, VOLT_RAIL);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			status);
@@ -461,7 +461,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
 		&g->perf_pmu.volt.volt_rail_metadata.volt_rails.super,
 			volt, VOLT, volt_rail, VOLT_RAIL);
-	if (status) {
+	if (status != 0) {
 		nvgpu_err(g,
 			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
 			status);
@@ -473,7 +473,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 			       volt_rails.super),
 			     struct voltage_rail *, pvolt_rail, i) {
 		status = volt_rail_state_init(g, pvolt_rail);
-		if (status) {
+		if (status != 0) {
 			nvgpu_err(g,
 				"Failure while executing RAIL's state init railIdx = %d",
 				i);
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h
index c73f315d9..c10cf5ca8 100644
--- a/drivers/gpu/nvgpu/volt/volt_rail.h
+++ b/drivers/gpu/nvgpu/volt/volt_rail.h
@@ -80,7 +80,7 @@ struct voltage_rail_metadata {
 u8 volt_rail_vbios_volt_domain_convert_to_internal
 	(struct gk20a *g, u8 vbios_volt_domain);
 
-u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
+int volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
 	*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
 
 u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);