From a3a508c21dda26e263745694b79df91b29dfb16d Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Mar 2019 15:52:23 +0530 Subject: [PATCH] gpu: nvgpu: move gr.commit_global_timeslice hal to hal.gr.init unit Move g->ops.gr.commit_global_timeslice() hal operation to hal.gr.init unit as g->ops.gr.init.commit_global_timeslice() Drop channel pointer in parameter list since it was unused Also change return type to void since it never returns error Move corresponding gm20b and gv11b hal operations to hal.gr.init unit Jira NVGPU-2961 Change-Id: I68deef45af1d52149eb354a1478cc2b5f2e4ec2a Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2075228 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 1 - .../nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 39 +---------------- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 - drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 +- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 42 ------------------ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 43 +++++++++++++++++++ drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h | 1 + drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c | 37 ++++++++++++++++ drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 3 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 3 +- 16 files changed, 94 insertions(+), 92 deletions(-) diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 176043c2e..a045b1a45 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -170,7 +170,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .program_sm_id_numbering = NULL, .setup_rop_mapping = NULL, .program_zcull_mapping = NULL, - .commit_global_timeslice = NULL, .commit_inst = vgpu_gr_commit_inst, .load_tpc_mask = NULL, .trigger_suspend = NULL, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index dd5980523..a52a9380c 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -188,7 +188,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .program_sm_id_numbering = NULL, .setup_rop_mapping = NULL, .program_zcull_mapping = NULL, - .commit_global_timeslice = NULL, .commit_inst = vgpu_gr_commit_inst, .load_tpc_mask = NULL, .trigger_suspend = NULL, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6c1699ae6..dbb68e391 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -732,43 +732,6 @@ int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, return 0; } -int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) -{ - struct nvgpu_gr_ctx *gr_ctx = NULL; - u32 gpm_pd_cfg; - u32 pd_ab_dist_cfg0; - u32 ds_debug; - u32 mpc_vtg_debug; - u32 pe_vaf; - u32 pe_vsc_vpc; - - nvgpu_log_fn(g, " "); - - gpm_pd_cfg = gk20a_readl(g, gr_gpcs_gpm_pd_cfg_r()); - pd_ab_dist_cfg0 = gk20a_readl(g, gr_pd_ab_dist_cfg0_r()); - ds_debug = gk20a_readl(g, gr_ds_debug_r()); - mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); - - pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); - pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); - - gpm_pd_cfg = gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() | gpm_pd_cfg; - pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; - pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | pe_vsc_vpc; - pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | pd_ab_dist_cfg0; - ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; - mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | mpc_vtg_debug; - - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gpm_pd_cfg_r(), gpm_pd_cfg, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), pe_vsc_vpc, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_ab_dist_cfg0_r(), pd_ab_dist_cfg0, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_ds_debug_r(), ds_debug, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), mpc_vtg_debug, false); - - return 0; -} - int gr_gk20a_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) { u32 norm_entries, norm_shift; @@ -1105,7 +1068,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g, } /* override a few ctx state registers */ - g->ops.gr.commit_global_timeslice(g, c); + g->ops.gr.init.commit_global_timeslice(g); /* floorsweep anything left */ err = nvgpu_gr_init_fs_state(g); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 1af912912..6698ae27c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -504,8 +504,6 @@ int gr_gk20a_resume_from_pause(struct gk20a *g); int gr_gk20a_clear_sm_errors(struct gk20a *g); u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); -int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); - int gr_gk20a_init_sm_id_table(struct gk20a *g); int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index b4cc98018..cd3c6e016 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -293,7 +293,6 @@ static const struct gpu_ops gm20b_ops = { .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, .setup_rop_mapping = gr_gk20a_setup_rop_mapping, .program_zcull_mapping = gr_gk20a_program_zcull_mapping, - .commit_global_timeslice = gr_gk20a_commit_global_timeslice, .commit_inst = gr_gk20a_commit_inst, .load_tpc_mask = gr_gm20b_load_tpc_mask, .trigger_suspend = gr_gk20a_trigger_suspend, @@ -434,6 +433,8 @@ static const struct gpu_ops gm20b_ops = { gm20b_gr_init_override_context_reset, .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, .load_method_init = gm20b_gr_init_load_method_init, + .commit_global_timeslice = + gm20b_gr_init_commit_global_timeslice, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 0ed81b9dc..e9acfcaa3 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -315,7 +315,6 @@ static const struct gpu_ops gp10b_ops = { .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, .setup_rop_mapping = gr_gk20a_setup_rop_mapping, .program_zcull_mapping = gr_gk20a_program_zcull_mapping, - .commit_global_timeslice = gr_gk20a_commit_global_timeslice, .commit_inst = gr_gk20a_commit_inst, .load_tpc_mask = gr_gm20b_load_tpc_mask, .trigger_suspend = gr_gk20a_trigger_suspend, @@ -506,6 +505,8 @@ static const struct gpu_ops gp10b_ops = { .preemption_state = gp10b_gr_init_preemption_state, .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, .load_method_init = gm20b_gr_init_load_method_init, + .commit_global_timeslice = + gm20b_gr_init_commit_global_timeslice, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7685cabcf..dc09f0c13 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -422,7 +422,6 @@ static const struct gpu_ops gv100_ops = { .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .setup_rop_mapping = gr_gv11b_setup_rop_mapping, .program_zcull_mapping = gr_gv11b_program_zcull_mapping, - .commit_global_timeslice = gr_gv11b_commit_global_timeslice, .commit_inst = gr_gv11b_commit_inst, .load_tpc_mask = gr_gv11b_load_tpc_mask, .trigger_suspend = gv11b_gr_sm_trigger_suspend, @@ -641,6 +640,8 @@ static const struct gpu_ops gv100_ops = { gm20b_gr_init_override_context_reset, .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, .load_method_init = gm20b_gr_init_load_method_init, + .commit_global_timeslice = + gv11b_gr_init_commit_global_timeslice, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 526c9cc2f..337314b85 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2776,48 +2776,6 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) return 0; } - - -int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) -{ - struct nvgpu_gr_ctx *ch_ctx = NULL; - u32 pd_ab_dist_cfg0; - u32 ds_debug; - u32 mpc_vtg_debug; - u32 pe_vaf; - u32 pe_vsc_vpc; - - nvgpu_log_fn(g, " "); - - pd_ab_dist_cfg0 = gk20a_readl(g, gr_pd_ab_dist_cfg0_r()); - ds_debug = gk20a_readl(g, gr_ds_debug_r()); - mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); - - pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); - pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); - - pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; - pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | - pe_vsc_vpc; - pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | - pd_ab_dist_cfg0; - ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; - mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | - mpc_vtg_debug; - - nvgpu_gr_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, - false); - nvgpu_gr_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), - pe_vsc_vpc, false); - nvgpu_gr_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(), - pd_ab_dist_cfg0, false); - nvgpu_gr_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, false); - nvgpu_gr_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), - mpc_vtg_debug, false); - - return 0; -} - void gr_gv11b_load_tpc_mask(struct gk20a *g) { u32 pes_tpc_mask = 0, fuse_tpc_mask; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 10f2c8b59..0ff1c74db 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -128,7 +128,6 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv11b_load_smid_config(struct gk20a *g); int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); -int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); void gr_gv11b_load_tpc_mask(struct gk20a *g); void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 350768641..74cd22885 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -374,7 +374,6 @@ static const struct gpu_ops gv11b_ops = { .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .setup_rop_mapping = gr_gv11b_setup_rop_mapping, .program_zcull_mapping = gr_gv11b_program_zcull_mapping, - .commit_global_timeslice = gr_gv11b_commit_global_timeslice, .commit_inst = gr_gv11b_commit_inst, .load_tpc_mask = gr_gv11b_load_tpc_mask, .trigger_suspend = gv11b_gr_sm_trigger_suspend, @@ -601,6 +600,8 @@ static const struct gpu_ops gv11b_ops = { .preemption_state = gv11b_gr_init_preemption_state, .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, .load_method_init = gm20b_gr_init_load_method_init, + .commit_global_timeslice = + gv11b_gr_init_commit_global_timeslice, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index 799e7a7c0..c7df0967a 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -331,3 +332,45 @@ void gm20b_gr_init_load_method_init(struct gk20a *g, sw_method_init->l[i].addr); } } + +void gm20b_gr_init_commit_global_timeslice(struct gk20a *g) +{ + u32 gpm_pd_cfg; + u32 pd_ab_dist_cfg0; + u32 ds_debug; + u32 mpc_vtg_debug; + u32 pe_vaf; + u32 pe_vsc_vpc; + + nvgpu_log_fn(g, " "); + + gpm_pd_cfg = nvgpu_readl(g, gr_gpcs_gpm_pd_cfg_r()); + pd_ab_dist_cfg0 = nvgpu_readl(g, gr_pd_ab_dist_cfg0_r()); + ds_debug = nvgpu_readl(g, gr_ds_debug_r()); + mpc_vtg_debug = nvgpu_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); + + pe_vaf = nvgpu_readl(g, gr_gpcs_tpcs_pe_vaf_r()); + pe_vsc_vpc = nvgpu_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); + + gpm_pd_cfg = gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() | gpm_pd_cfg; + pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; + pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | + pe_vsc_vpc; + pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | + pd_ab_dist_cfg0; + ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; + mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | + mpc_vtg_debug; + + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_gpm_pd_cfg_r(), gpm_pd_cfg, + false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, + false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_pes_vsc_vpc_r(), + pe_vsc_vpc, false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_pd_ab_dist_cfg0_r(), + pd_ab_dist_cfg0, false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_mpc_vtg_debug_r(), + mpc_vtg_debug, false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_ds_debug_r(), ds_debug, false); +} diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index d26c8e46d..5c47f9229 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -40,5 +40,6 @@ void gm20b_gr_init_override_context_reset(struct gk20a *g); void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable); void gm20b_gr_init_load_method_init(struct gk20a *g, struct netlist_av_list *sw_method_init); +void gm20b_gr_init_commit_global_timeslice(struct gk20a *g); #endif /* NVGPU_GR_INIT_GM20B_H */ diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c index e8306f7ed..f59af67b0 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "gr_init_gv11b.h" @@ -118,3 +119,39 @@ int gv11b_gr_init_preemption_state(struct gk20a *g, u32 gfxp_wfi_timeout_count, return 0; } +void gv11b_gr_init_commit_global_timeslice(struct gk20a *g) +{ + u32 pd_ab_dist_cfg0; + u32 ds_debug; + u32 mpc_vtg_debug; + u32 pe_vaf; + u32 pe_vsc_vpc; + + nvgpu_log_fn(g, " "); + + pd_ab_dist_cfg0 = nvgpu_readl(g, gr_pd_ab_dist_cfg0_r()); + ds_debug = nvgpu_readl(g, gr_ds_debug_r()); + mpc_vtg_debug = nvgpu_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); + + pe_vaf = nvgpu_readl(g, gr_gpcs_tpcs_pe_vaf_r()); + pe_vsc_vpc = nvgpu_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); + + pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; + pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | + pe_vsc_vpc; + pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | + pd_ab_dist_cfg0; + ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; + mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | + mpc_vtg_debug; + + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, + false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_pes_vsc_vpc_r(), + pe_vsc_vpc, false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_pd_ab_dist_cfg0_r(), + pd_ab_dist_cfg0, false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_gpcs_tpcs_mpc_vtg_debug_r(), + mpc_vtg_debug, false); + nvgpu_gr_ctx_patch_write(g, NULL, gr_ds_debug_r(), ds_debug, false); +} diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h index c527e749a..f1784f7a5 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h @@ -30,5 +30,6 @@ struct gk20a; int gv11b_gr_init_fs_state(struct gk20a *g); int gv11b_gr_init_preemption_state(struct gk20a *g, u32 gfxp_wfi_timeout_count, bool gfxp_wfi_timeout_unit_usec); +void gv11b_gr_init_commit_global_timeslice(struct gk20a *g); #endif /* NVGPU_GR_INIT_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 9e600f150..e77aecc9b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -434,8 +434,6 @@ struct gpu_ops { int (*init_sw_veid_bundle)(struct gk20a *g); void (*program_zcull_mapping)(struct gk20a *g, u32 zcull_alloc_num, u32 *zcull_map_tiles); - int (*commit_global_timeslice)(struct gk20a *g, - struct channel_gk20a *c); int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va); void (*set_preemption_buffer_va)(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va); @@ -689,6 +687,7 @@ struct gpu_ops { bool enable); void (*load_method_init)(struct gk20a *g, struct netlist_av_list *sw_method_init); + void (*commit_global_timeslice)(struct gk20a *g); } init; u32 (*get_ctxsw_checksum_mismatch_mailbox_val)(void); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 08e724f24..8683b3d38 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -441,7 +441,6 @@ static const struct gpu_ops tu104_ops = { .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .setup_rop_mapping = gr_gv11b_setup_rop_mapping, .program_zcull_mapping = gr_gv11b_program_zcull_mapping, - .commit_global_timeslice = gr_gv11b_commit_global_timeslice, .commit_inst = gr_gv11b_commit_inst, .load_tpc_mask = gr_gv11b_load_tpc_mask, .trigger_suspend = gv11b_gr_sm_trigger_suspend, @@ -669,6 +668,8 @@ static const struct gpu_ops tu104_ops = { .preemption_state = gv11b_gr_init_preemption_state, .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, .load_method_init = gm20b_gr_init_load_method_init, + .commit_global_timeslice = + gv11b_gr_init_commit_global_timeslice, }, }, .fb = {