diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 5c09aac83..d84f7c97d 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -474,8 +474,10 @@ int gk20a_finalize_poweron(struct gk20a *g) g->ops.chip_init_gpu_characteristics(g); +#ifdef CONFIG_NVGPU_DEBUGGER /* Restore the debug setting */ g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl); +#endif #ifdef CONFIG_NVGPU_CE err = nvgpu_ce_init_support(g); diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index ba29cef50..b95d8a64e 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -394,8 +394,10 @@ static const struct gpu_ops vgpu_gp10b_ops = { .dump_vpr_info = NULL, .dump_wpr_info = NULL, .read_wpr_info = NULL, +#ifdef CONFIG_NVGPU_DEBUGGER .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, +#endif .tlb_invalidate = vgpu_mm_tlb_invalidate, }, .cg = { diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index c244cfa75..e1c33f5a3 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -460,8 +460,10 @@ static const struct gpu_ops vgpu_gv11b_ops = { .dump_vpr_info = NULL, .dump_wpr_info = NULL, .read_wpr_info = NULL, +#ifdef CONFIG_NVGPU_DEBUGGER .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, +#endif .tlb_invalidate = vgpu_mm_tlb_invalidate, .write_mmu_fault_buffer_lo_hi = gv11b_fb_write_mmu_fault_buffer_lo_hi, diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c index 3359ce6d3..524c6b7a4 100644 --- a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c @@ -214,6 +214,7 @@ int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) return 0; } +#ifdef CONFIG_NVGPU_DEBUGGER void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) { struct tegra_vgpu_cmd_msg msg; @@ -228,6 +229,7 @@ void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); } +#endif static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, u64 addr, u64 size, size_t *oob_size) diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h index 074a1c871..00342cb0b 100644 --- a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h @@ -46,7 +46,9 @@ int vgpu_mm_fb_flush(struct gk20a *g); void vgpu_mm_l2_invalidate(struct gk20a *g); int vgpu_mm_l2_flush(struct gk20a *g, bool invalidate); int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); +#ifdef CONFIG_NVGPU_DEBUGGER void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable); +#endif u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, u64 map_offset, struct nvgpu_sgt *sgt, diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c index 95d16b1f0..940ea4efb 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c @@ -326,6 +326,7 @@ void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size) *wpr_size = (wpr_end - wpr_start); } +#ifdef CONFIG_NVGPU_DEBUGGER bool gm20b_fb_debug_mode_enabled(struct gk20a *g) { u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); @@ -350,7 +351,6 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); -#ifdef CONFIG_NVGPU_DEBUGGER g->ops.gr.set_debug_mode(g, enable); -#endif } +#endif diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.h b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.h index 22c58a3f2..751e59a67 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.h +++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.h @@ -48,7 +48,9 @@ void gm20b_fb_dump_vpr_info(struct gk20a *g); void gm20b_fb_dump_wpr_info(struct gk20a *g); void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size); int gm20b_fb_vpr_info_fetch(struct gk20a *g); +#ifdef CONFIG_NVGPU_DEBUGGER bool gm20b_fb_debug_mode_enabled(struct gk20a *g); void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable); +#endif #endif diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index f03a1ec71..052fb6bfd 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -537,8 +537,10 @@ static const struct gpu_ops gm20b_ops = { .dump_vpr_info = gm20b_fb_dump_vpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, +#ifdef CONFIG_NVGPU_DEBUGGER .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, +#endif .tlb_invalidate = gm20b_fb_tlb_invalidate, .mem_unlock = NULL, }, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 191333dc5..13f22b49a 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -606,8 +606,10 @@ static const struct gpu_ops gp10b_ops = { .dump_vpr_info = gm20b_fb_dump_vpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, +#ifdef CONFIG_NVGPU_DEBUGGER .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, +#endif .tlb_invalidate = gm20b_fb_tlb_invalidate, .mem_unlock = NULL, }, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index d21aae5aa..aa6b10c9a 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -713,8 +713,10 @@ static const struct gpu_ops gv11b_ops = { .dump_vpr_info = gm20b_fb_dump_vpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, +#ifdef CONFIG_NVGPU_DEBUGGER .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, +#endif .tlb_invalidate = gm20b_fb_tlb_invalidate, .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, .mem_unlock = NULL, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 1ed1bc66c..42c82a3cc 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -749,8 +749,10 @@ static const struct gpu_ops tu104_ops = { .dump_vpr_info = NULL, .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, +#ifdef CONFIG_NVGPU_DEBUGGER .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, +#endif .tlb_invalidate = fb_tu104_tlb_invalidate, .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, .mem_unlock = gv100_fb_memory_unlock, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 2c20b2c60..c877f68cd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -921,8 +921,10 @@ struct gpu_ops { void (*dump_wpr_info)(struct gk20a *g); int (*vpr_info_fetch)(struct gk20a *g); void (*read_wpr_info)(struct gk20a *g, u64 *wpr_base, u64 *wpr_size); +#ifdef CONFIG_NVGPU_DEBUGGER bool (*is_debug_mode_enabled)(struct gk20a *g); void (*set_debug_mode)(struct gk20a *g, bool enable); +#endif int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); void (*handle_replayable_fault)(struct gk20a *g); int (*mem_unlock)(struct gk20a *g);