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gpu: nvgpu: add tegra_raw support

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* This change adds NVGPU_AS_MAP_BUFFER_FLAGS_TEGRA_RAW flag
   to control buffer format
 * Add NVGPU_SUPPORT_TEGRA_RAW enabled flag to indicate if feature
   is enabled for a given chip.
 * Update gv11b_gpu_phys_addr function to set TEGRA_RAW bit

Jira NVGPU-6640
Bug 3489827

Change-Id: I959c22bef906bb9c6dcdc8d5f5e9951ad9937a60
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2545128
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kadamati
2021-06-15 12:11:21 +05:30
committed by mobile promotions
parent 03b1a81ab1
commit a3ed73a57c
8 changed files with 63 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/enabled.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -217,6 +217,8 @@ struct gk20a;
DEFINE_FLAG(NVGPU_SUPPORT_ROP_IN_GPC, "ROP is part of GPC"), \
DEFINE_FLAG(NVGPU_SUPPORT_BUFFER_METADATA, "Buffer metadata support"), \
DEFINE_FLAG(NVGPU_SUPPORT_NVS, "Domain scheduler support"), \
DEFINE_FLAG(NVGPU_SUPPORT_TEGRA_RAW, \
"TEGRA_RAW format support"), \
DEFINE_FLAG(NVGPU_MAX_ENABLED_BITS, "Marks max number of flags"),
/**

6
drivers/gpu/nvgpu/include/nvgpu/gmmu.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -175,6 +175,10 @@ struct nvgpu_gmmu_attrs {
* True if l3_alloc flag is valid.
*/
bool l3_alloc;
/**
* True if tegra_raw flag is valid.
*/
bool tegra_raw;
/**
* True if platform_atomic flag is valid.
*/

13
drivers/gpu/nvgpu/include/nvgpu/gops/mm.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -352,6 +352,17 @@ struct gops_mm_gmmu {
*/
u32 (*get_iommu_bit)(struct gk20a *g);
/**
* @brief HAL to get the tegra_raw physical bit position.
*
* @param g [in] The GPU.
*
* This HAL is used to get the tegra_raw physical bit position.
*
* @return tegra_raw physical bit position.
*/
u32 (*get_gpu_phys_tegra_raw_bit)(struct gk20a *g);
/**
* @brief HAL to convert from tegra_phys to gpu_phys.
*

3
drivers/gpu/nvgpu/include/nvgpu/vm.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -350,6 +350,7 @@ struct vm_gk20a {
#define NVGPU_VM_MAP_DIRECT_KIND_CTRL BIT32(4)
#define NVGPU_VM_MAP_L3_ALLOC BIT32(5)
#define NVGPU_VM_MAP_PLATFORM_ATOMIC BIT32(6)
#define NVGPU_VM_MAP_TEGRA_RAW BIT32(7)
#define NVGPU_VM_MAP_ACCESS_DEFAULT 0U
#define NVGPU_VM_MAP_ACCESS_READ_ONLY 1U