diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
index 033d3fcdc..7d4e638a5 100644
--- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c
+++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
@@ -42,7 +42,7 @@ int nvgpu_init_gr_manager(struct gk20a *g)
 	int err = 0;
 	const struct nvgpu_device *gr_dev = NULL;
 
-#ifdef CONFIG_NVGPU_NON_FUSA
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 	if (g->ops.grmgr.load_timestamp_prod != NULL) {
 		g->ops.grmgr.load_timestamp_prod(g);
 	}
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
index d8c175de0..f47693fca 100644
--- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c
@@ -1,7 +1,7 @@
 /*
  * GA10B GR MANAGER
  *
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -967,6 +967,7 @@ int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
 
 #endif
 
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
 {
 	u32 reg_val;
@@ -979,6 +980,7 @@ void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g)
 	nvgpu_writel(g, smcarb_timestamp_ctrl_r(), reg_val);
 
 }
+#endif
 
 int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
 		u32 num_gpc, struct nvgpu_gpc *gpcs)
diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
index cf66591f3..dc97c6c1f 100644
--- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.h
@@ -1,7 +1,7 @@
 /*
  * GA10B GR MANAGER
  *
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -42,7 +42,9 @@ int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
 void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g);
 #endif
 
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g);
+#endif
 int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
 		u32 num_gpc, struct nvgpu_gpc *gpcs);
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index 5e4163121..3f5068962 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -1,7 +1,7 @@
 /*
  * GA100 Tegra HAL interface
  *
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1722,7 +1722,7 @@ static const struct gops_grmgr ga100_ops_grmgr = {
 #else
 	.init_gr_manager = nvgpu_init_gr_manager,
 #endif
-#ifdef CONFIG_NVGPU_NON_FUSA
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
 #endif
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index dee8e921b..83f61258a 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1,7 +1,7 @@
 /*
  * GA10B Tegra HAL interface
  *
- * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1699,7 +1699,7 @@ static const struct gops_grmgr ga10b_ops_grmgr = {
 #else
 	.init_gr_manager = nvgpu_init_gr_manager,
 #endif
-#ifdef CONFIG_NVGPU_NON_FUSA
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
 	.load_timestamp_prod = ga10b_grmgr_load_smc_arb_timestamp_prod,
 #endif
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,