diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 4940f5a6e..ff8ecf5bc 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1365,6 +1365,16 @@ static const struct gops_pmu ga100_ops_pmu = { .get_exterrstat = gk20a_pmu_get_exterrstat, .set_exterrstat = gk20a_pmu_set_exterrstat, .get_exterraddr = gk20a_pmu_get_exterraddr, + .get_bar0_addr = gk20a_pmu_get_bar0_addr, + .get_bar0_data = gk20a_pmu_get_bar0_data, + .get_bar0_timeout = gk20a_pmu_get_bar0_timeout, + .get_bar0_ctl = gk20a_pmu_get_bar0_ctl, + .get_bar0_error_status = gk20a_pmu_get_bar0_error_status, + .set_bar0_error_status = gk20a_pmu_set_bar0_error_status, + .get_bar0_fecs_error = gk20a_pmu_get_bar0_fecs_error, + .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, + .get_mailbox = gk20a_pmu_get_mailbox, + .get_pmu_debug = gk20a_pmu_get_pmu_debug, .pmu_isr = gk20a_pmu_isr, .pmu_init_perfmon_counter = ga10b_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 86d334d74..46033a27e 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1419,6 +1419,16 @@ static const struct gops_pmu ga10b_ops_pmu = { .get_exterrstat = gk20a_pmu_get_exterrstat, .set_exterrstat = gk20a_pmu_set_exterrstat, .get_exterraddr = gk20a_pmu_get_exterraddr, + .get_bar0_addr = gk20a_pmu_get_bar0_addr, + .get_bar0_data = gk20a_pmu_get_bar0_data, + .get_bar0_timeout = gk20a_pmu_get_bar0_timeout, + .get_bar0_ctl = gk20a_pmu_get_bar0_ctl, + .get_bar0_error_status = gk20a_pmu_get_bar0_error_status, + .set_bar0_error_status = gk20a_pmu_set_bar0_error_status, + .get_bar0_fecs_error = gk20a_pmu_get_bar0_fecs_error, + .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, + .get_mailbox = gk20a_pmu_get_mailbox, + .get_pmu_debug = gk20a_pmu_get_pmu_debug, #ifdef CONFIG_NVGPU_LS_PMU .pmu_seq_cleanup = nvgpu_pmu_seq_free_release, .get_inst_block_config = ga10b_pmu_get_inst_block_config, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 582d80976..139d9ede8 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -866,6 +866,16 @@ static const struct gops_pmu gm20b_ops_pmu = { .get_exterrstat = gk20a_pmu_get_exterrstat, .set_exterrstat = gk20a_pmu_set_exterrstat, .get_exterraddr = gk20a_pmu_get_exterraddr, + .get_bar0_addr = gk20a_pmu_get_bar0_addr, + .get_bar0_data = gk20a_pmu_get_bar0_data, + .get_bar0_timeout = gk20a_pmu_get_bar0_timeout, + .get_bar0_ctl = gk20a_pmu_get_bar0_ctl, + .get_bar0_error_status = gk20a_pmu_get_bar0_error_status, + .set_bar0_error_status = gk20a_pmu_set_bar0_error_status, + .get_bar0_fecs_error = gk20a_pmu_get_bar0_fecs_error, + .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, + .get_mailbox = gk20a_pmu_get_mailbox, + .get_pmu_debug = gk20a_pmu_get_pmu_debug, .pmu_isr = gk20a_pmu_isr, .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 0c9130587..3e4a255e2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -1179,6 +1179,16 @@ static const struct gops_pmu gv11b_ops_pmu = { .get_exterrstat = gk20a_pmu_get_exterrstat, .set_exterrstat = gk20a_pmu_set_exterrstat, .get_exterraddr = gk20a_pmu_get_exterraddr, + .get_bar0_addr = gk20a_pmu_get_bar0_addr, + .get_bar0_data = gk20a_pmu_get_bar0_data, + .get_bar0_timeout = gk20a_pmu_get_bar0_timeout, + .get_bar0_ctl = gk20a_pmu_get_bar0_ctl, + .get_bar0_error_status = gk20a_pmu_get_bar0_error_status, + .set_bar0_error_status = gk20a_pmu_set_bar0_error_status, + .get_bar0_fecs_error = gk20a_pmu_get_bar0_fecs_error, + .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, + .get_mailbox = gk20a_pmu_get_mailbox, + .get_pmu_debug = gk20a_pmu_get_pmu_debug, .pmu_isr = gk20a_pmu_isr, .handle_ext_irq = gv11b_pmu_handle_ext_irq, #ifdef CONFIG_NVGPU_LS_PMU diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 321068854..a0c6a2545 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1242,6 +1242,16 @@ static const struct gops_pmu tu104_ops_pmu = { .get_exterrstat = gk20a_pmu_get_exterrstat, .set_exterrstat = gk20a_pmu_set_exterrstat, .get_exterraddr = gk20a_pmu_get_exterraddr, + .get_bar0_addr = gk20a_pmu_get_bar0_addr, + .get_bar0_data = gk20a_pmu_get_bar0_data, + .get_bar0_timeout = gk20a_pmu_get_bar0_timeout, + .get_bar0_ctl = gk20a_pmu_get_bar0_ctl, + .get_bar0_error_status = gk20a_pmu_get_bar0_error_status, + .set_bar0_error_status = gk20a_pmu_set_bar0_error_status, + .get_bar0_fecs_error = gk20a_pmu_get_bar0_fecs_error, + .set_bar0_fecs_error = gk20a_pmu_set_bar0_fecs_error, + .get_mailbox = gk20a_pmu_get_mailbox, + .get_pmu_debug = gk20a_pmu_get_pmu_debug, .pmu_isr = gk20a_pmu_isr, .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c index 603b45fa8..ec19e7df3 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c @@ -43,28 +43,28 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) for (i = 0; i < pwr_pmu_mailbox__size_1_v(); i++) { nvgpu_err(g, "pwr_pmu_mailbox_r(%d) : 0x%x", - i, gk20a_readl(g, pwr_pmu_mailbox_r(i))); + i, g->ops.pmu.get_mailbox(g, i)); } for (i = 0; i < pwr_pmu_debug__size_1_v(); i++) { nvgpu_err(g, "pwr_pmu_debug_r(%d) : 0x%x", - i, gk20a_readl(g, pwr_pmu_debug_r(i))); + i, g->ops.pmu.get_pmu_debug(g, i)); } - i = gk20a_readl(g, pwr_pmu_bar0_error_status_r()); + i = g->ops.pmu.get_bar0_error_status(g); nvgpu_err(g, "pwr_pmu_bar0_error_status_r : 0x%x", i); if (i != 0U) { nvgpu_err(g, "pwr_pmu_bar0_addr_r : 0x%x", - gk20a_readl(g, pwr_pmu_bar0_addr_r())); + g->ops.pmu.get_bar0_addr(g)); nvgpu_err(g, "pwr_pmu_bar0_data_r : 0x%x", - gk20a_readl(g, pwr_pmu_bar0_data_r())); + g->ops.pmu.get_bar0_data(g)); nvgpu_err(g, "pwr_pmu_bar0_timeout_r : 0x%x", - gk20a_readl(g, pwr_pmu_bar0_timeout_r())); + g->ops.pmu.get_bar0_timeout(g)); nvgpu_err(g, "pwr_pmu_bar0_ctl_r : 0x%x", - gk20a_readl(g, pwr_pmu_bar0_ctl_r())); + g->ops.pmu.get_bar0_ctl(g)); } - i = gk20a_readl(g, pwr_pmu_bar0_fecs_error_r()); + i = g->ops.pmu.get_bar0_fecs_error(g); nvgpu_err(g, "pwr_pmu_bar0_fecs_error_r : 0x%x", i); i = g->ops.pmu.get_exterrstat(g); @@ -502,7 +502,7 @@ void gk20a_pmu_handle_interrupts(struct gk20a *g, u32 intr) if ((intr & pwr_falcon_irqstat_halt_true_f()) != 0U) { nvgpu_err(g, "pmu halt intr not implemented"); nvgpu_pmu_dump_falcon_stats(pmu); - if (nvgpu_readl(g, pwr_pmu_mailbox_r + if (g->ops.pmu.get_mailbox(g, (PMU_MODE_MISMATCH_STATUS_MAILBOX_R)) == PMU_MODE_MISMATCH_STATUS_VAL) { if (g->ops.pmu.dump_secure_fuses != NULL) { @@ -576,7 +576,7 @@ int gk20a_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, u32 err_status = 0; u32 err_cmd = 0; - val = gk20a_readl(g, pwr_pmu_bar0_error_status_r()); + val = g->ops.pmu.get_bar0_error_status(g); *bar0_status = val; if (val == 0U) { return 0; @@ -592,14 +592,14 @@ int gk20a_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, *etype = pmu_bar0_cmd_hwerr_etype(err_cmd); } else if ((val & pwr_pmu_bar0_error_status_fecserr_m()) != 0U) { *etype = pmu_bar0_fecserr_etype(err_cmd); - err_status = gk20a_readl(g, pwr_pmu_bar0_fecs_error_r()); + err_status = g->ops.pmu.get_bar0_fecs_error(g); /* * BAR0_FECS_ERROR would only record the first error code if * multiple FECS error happen. Once BAR0_FECS_ERROR is cleared, * BAR0_FECS_ERROR can record the error code from FECS again. * Writing status regiter to clear the FECS Hardware state. */ - gk20a_writel(g, pwr_pmu_bar0_fecs_error_r(), err_status); + g->ops.pmu.set_bar0_fecs_error(g, err_status); } else if ((val & pwr_pmu_bar0_error_status_hosterr_m()) != 0U) { *etype = pmu_bar0_hosterr_etype(err_cmd); /* @@ -619,7 +619,7 @@ int gk20a_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, } /* Writing Bar0 status regiter to clear the Hardware state */ - gk20a_writel(g, pwr_pmu_bar0_error_status_r(), val); + g->ops.pmu.set_bar0_error_status(g, val); return (-EIO); } diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h index eaef66c73..5a2308a64 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h @@ -40,6 +40,16 @@ void gk20a_pmu_set_irqsset(struct gk20a *g, u32 intr); u32 gk20a_pmu_get_exterrstat(struct gk20a *g); void gk20a_pmu_set_exterrstat(struct gk20a *g, u32 intr); u32 gk20a_pmu_get_exterraddr(struct gk20a *g); +u32 gk20a_pmu_get_bar0_addr(struct gk20a *g); +u32 gk20a_pmu_get_bar0_data(struct gk20a *g); +u32 gk20a_pmu_get_bar0_timeout(struct gk20a *g); +u32 gk20a_pmu_get_bar0_ctl(struct gk20a *g); +u32 gk20a_pmu_get_bar0_error_status(struct gk20a *g); +void gk20a_pmu_set_bar0_error_status(struct gk20a *g, u32 val); +u32 gk20a_pmu_get_bar0_fecs_error(struct gk20a *g); +void gk20a_pmu_set_bar0_fecs_error(struct gk20a *g, u32 val); +u32 gk20a_pmu_get_mailbox(struct gk20a *g, u32 i); +u32 gk20a_pmu_get_pmu_debug(struct gk20a *g, u32 i); #ifdef CONFIG_NVGPU_LS_PMU void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c index 2ff403761..dc32671cb 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c @@ -68,6 +68,56 @@ u32 gk20a_pmu_get_exterraddr(struct gk20a *g) return nvgpu_readl(g, pwr_falcon_exterraddr_r()); } +u32 gk20a_pmu_get_bar0_addr(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_bar0_addr_r()); +} + +u32 gk20a_pmu_get_bar0_data(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_bar0_data_r()); +} + +u32 gk20a_pmu_get_bar0_timeout(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_bar0_timeout_r()); +} + +u32 gk20a_pmu_get_bar0_ctl(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_bar0_ctl_r()); +} + +u32 gk20a_pmu_get_bar0_error_status(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_bar0_error_status_r()); +} + +void gk20a_pmu_set_bar0_error_status(struct gk20a *g, u32 val) +{ + return nvgpu_writel(g, pwr_pmu_bar0_error_status_r(), val); +} + +u32 gk20a_pmu_get_bar0_fecs_error(struct gk20a *g) +{ + return nvgpu_readl(g, pwr_pmu_bar0_fecs_error_r()); +} + +void gk20a_pmu_set_bar0_fecs_error(struct gk20a *g, u32 val) +{ + return nvgpu_writel(g, pwr_pmu_bar0_fecs_error_r(), val); +} + +u32 gk20a_pmu_get_mailbox(struct gk20a *g, u32 i) +{ + return nvgpu_readl(g, pwr_pmu_mailbox_r(i)); +} + +u32 gk20a_pmu_get_pmu_debug(struct gk20a *g, u32 i) +{ + return nvgpu_readl(g, pwr_pmu_debug_r(i)); +} + void gk20a_pmu_isr(struct gk20a *g) { struct nvgpu_pmu *pmu = g->pmu; diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c index 1fa34812f..9119c9d97 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -88,7 +88,7 @@ int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, u32 err_status = 0; u32 err_cmd = 0; - val = nvgpu_readl(g, pwr_pmu_bar0_error_status_r()); + val = g->ops.pmu.get_bar0_error_status(g); *bar0_status = val; if (val == 0U) { return 0; @@ -104,14 +104,14 @@ int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, *etype = pmu_bar0_cmd_hwerr_etype(err_cmd); } else if ((val & pwr_pmu_bar0_error_status_fecserr_m()) != 0U) { *etype = pmu_bar0_fecserr_etype(err_cmd); - err_status = nvgpu_readl(g, pwr_pmu_bar0_fecs_error_r()); + err_status = g->ops.pmu.get_bar0_fecs_error(g); /* * BAR0_FECS_ERROR would only record the first error code if * multiple FECS error happen. Once BAR0_FECS_ERROR is cleared, * BAR0_FECS_ERROR can record the error code from FECS again. * Writing status regiter to clear the FECS Hardware state. */ - nvgpu_writel(g, pwr_pmu_bar0_fecs_error_r(), err_status); + g->ops.pmu.set_bar0_fecs_error(g, err_status); } else if ((val & pwr_pmu_bar0_error_status_hosterr_m()) != 0U) { *etype = pmu_bar0_hosterr_etype(err_cmd); /* @@ -131,7 +131,7 @@ int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status, } /* Writing Bar0 status regiter to clear the Hardware state */ - nvgpu_writel(g, pwr_pmu_bar0_error_status_r(), val); + g->ops.pmu.set_bar0_error_status(g, val); return (-EIO); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h index e8d3af29d..20bc58ae0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h @@ -479,6 +479,16 @@ struct gops_pmu { u32 (*get_exterrstat)(struct gk20a *g); void (*set_exterrstat)(struct gk20a *g, u32 intr); u32 (*get_exterraddr)(struct gk20a *g); + u32 (*get_bar0_addr)(struct gk20a *g); + u32 (*get_bar0_data)(struct gk20a *g); + u32 (*get_bar0_timeout)(struct gk20a *g); + u32 (*get_bar0_ctl)(struct gk20a *g); + u32 (*get_bar0_error_status)(struct gk20a *g); + void (*set_bar0_error_status)(struct gk20a *g, u32 val); + u32 (*get_bar0_fecs_error)(struct gk20a *g); + void (*set_bar0_fecs_error)(struct gk20a *g, u32 val); + u32 (*get_mailbox)(struct gk20a *g, u32 i); + u32 (*get_pmu_debug)(struct gk20a *g, u32 i); #ifdef CONFIG_NVGPU_LS_PMU u32 (*get_inst_block_config)(struct gk20a *g);