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gpu: nvgpu: Update doxygen comments for common.top

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Remove usage of informal words like "we" from the documentation
based on comments from SWUD-lite inspection.

JIRA NVGPU-4415

Change-Id: I8ad8b286392d55bb9fc00c82be3a39b19c1e3ad9
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263195
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
tkudav
2019-12-16 15:10:36 +05:30
committed by Alex Waterman
parent 2b36d309cc
commit a41d3da9b6
1 changed files with 11 additions and 11 deletions
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22
drivers/gpu/nvgpu/include/nvgpu/gops_top.h
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@@ -50,7 +50,7 @@ struct gops_top {
* corresponding to each instance of the engine. All such entries
* corresponding to same engine will have same \a engine_type, but
* a unique instance id.
* 2. We traverse through the device_info table and get the total
* 2. Traverse through the device_info table and get the total
* number of entries corresponding to input \a engine_type.
* 3. This HAL is valid for Pascal and chips beyond.
* 4. Prior to Pascal, each instance of the engine was denoted by a
@@ -93,25 +93,25 @@ struct gops_top {
* register talks the same engine as present the one. All the
* registers in the device info table can be classified in one of 4
* types:
* - Not_valid: We ignore these registers
* - Not_valid: Ignore these registers
* - Data: This type of register contains pri_base, fault_id etc
* - Enum: This type of register contains intr_enum, reset_enum
* - Engine_type: This type of register contains the engine name
* which is being described.
* 5. So, in the parsing code,
* - We loop through the array
* - Loop through the array
* - Ignore the invalid entries
* - Store the “linked” register values in temporary variables
* until chain_bit is set. This helps us get all the data for
* particular engine type. [This is needed because the engine
* name may not be part of the first register representing the
* engine. So we can’t just read the first register and
* determine if the group represents the engine we are
* interested in]. Once the chain_bit is disabled, we know the
* next register read would represent a new engine.
* - So we parse the stored variables to get engine_name,
* intr/reset_enums, pri base etc. Here we check if the engine
* type is the one we are interested in.
* engine. So, reading the first register is not sufficient to
* determine if the group represents the \a engine_type.
* Chain_bit being disabled implies the next register read
* would represent a new engine.
* - Parse the stored variables to get engine_name,
* intr/reset_enums, pri base etc. Check if the engine
* type read from the table equals \a engine_type.
*
* List of valid engine enumeration values:
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -184,7 +184,7 @@ struct gops_top {
* COPY_ENGINE_INSTANCE1 engine_type - 2
* COPY_ENGINE_INSTANCE2 engine_type - 3
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* 2. We calculate the instance id by subtracting COPY_ENGINE_INSTANCE0
* 2. Calculate the instance id by subtracting COPY_ENGINE_INSTANCE0
* enum value from \a engine_type.
*
* @return Calculated instance ID as explained above.