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gpu: nvgpu: WPR update

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- setting WPR at 188MB of VIDMEM
- setting 256/512MB location at
VIDMEM for WPR cause ACR boot failure
on GP104/GP106 PROD board but works fine
for DEBUG board,
- Removed unwanted WPR info dump

JIRA DNVGPU-34

Change-Id: I44f9861774fe77dd534d316d91ed9f8dfcb298b4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1164840
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-06-15 14:51:51 +05:30
committed by Deepak Nibade
parent 5da9567834
commit a445c27d5b
1 changed files with 2 additions and 5 deletions
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7
drivers/gpu/nvgpu/gp106/acr_gp106.c
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@@ -37,8 +37,8 @@ typedef int (*get_ucode_details)(struct gk20a *g,
/* Both size and address of WPR need to be 128K-aligned */ /* Both size and address of WPR need to be 128K-aligned */
#define WPR_ALIGNMENT 0x20000 #define WPR_ALIGNMENT 0x20000
#define GP106_DGPU_NONWPR 0x10000000 /* start from 256MB location at VIDMEM */ #define GP106_DGPU_NONWPR 0x18000000
#define GP106_DGPU_WPR 0x20000000 #define GP106_DGPU_WPR (GP106_DGPU_NONWPR + 0x400000)
#define DGPU_WPR_SIZE 0x100000 #define DGPU_WPR_SIZE 0x100000
/*Externs*/ /*Externs*/
@@ -365,9 +365,6 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
gm20b_mm_mmu_vpr_info_fetch(g); gm20b_mm_mmu_vpr_info_fetch(g);
gr_gk20a_init_ctxsw_ucode(g); gr_gk20a_init_ctxsw_ucode(g);
if (g->ops.fb.dump_vpr_wpr_info)
g->ops.fb.dump_vpr_wpr_info(g);
g->ops.pmu.get_wpr(g, &wpr_inf); g->ops.pmu.get_wpr(g, &wpr_inf);
gp106_dbg_pmu("wpr carveout base:%llx\n", (wpr_inf.wpr_base)); gp106_dbg_pmu("wpr carveout base:%llx\n", (wpr_inf.wpr_base));
gp106_dbg_pmu("wpr carveout size :%x\n", (u32)wpr_inf.size); gp106_dbg_pmu("wpr carveout size :%x\n", (u32)wpr_inf.size);