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gpu: nvgpu: Fix PG unit members direct access in other units

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Other units directly access PG unit members like:
pmu->pg->pg_buf

This direct access is fixed by introducing public
interface to handle this correctly

JIRA NVGPU-3405

Change-Id: I13f5922bb04ece680f4b487ffc8f1d11e4efd234
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118281
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-05-14 09:34:01 +05:30
committed by mobile promotions
parent e4c63e7b36
commit a46eca3483
3 changed files with 22 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/gr/gr_falcon.c
View File

@@ -97,8 +97,8 @@ int nvgpu_gr_falcon_bind_fecs_elpg(struct gk20a *g)
return err; return err;
} }
if (pmu->pg->pg_buf.cpu_va == NULL) { if (nvgpu_pmu_pg_buf_get_cpu_va(pmu) == NULL) {
err = nvgpu_dma_alloc_map_sys(vm, size, &pmu->pg->pg_buf); err = nvgpu_dma_alloc_map_sys(vm, size, nvgpu_pmu_pg_buf(pmu));
if (err != 0) { if (err != 0) {
nvgpu_err(g, "failed to allocate memory"); nvgpu_err(g, "failed to allocate memory");
return -ENOMEM; return -ENOMEM;
@@ -115,7 +115,7 @@ int nvgpu_gr_falcon_bind_fecs_elpg(struct gk20a *g)
return err; return err;
} }
data = u64_lo32(pmu->pg->pg_buf.gpu_va >> 8); data = u64_lo32(nvgpu_pmu_pg_buf_get_gpu_va(pmu) >> 8);
err = g->ops.gr.falcon.ctrl_ctxsw(g, err = g->ops.gr.falcon.ctrl_ctxsw(g,
NVGPU_GR_FALCON_METHOD_REGLIST_SET_VIRTUAL_ADDRESS, data, NULL); NVGPU_GR_FALCON_METHOD_REGLIST_SET_VIRTUAL_ADDRESS, data, NULL);
if (err != 0) { if (err != 0) {

15
drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
View File

@@ -1094,3 +1094,18 @@ bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id)
return pmu->pg->is_lpwr_feature_supported(g, feature_id); return pmu->pg->is_lpwr_feature_supported(g, feature_id);
} }
u64 nvgpu_pmu_pg_buf_get_gpu_va(struct nvgpu_pmu *pmu)
{
return pmu->pg->pg_buf.gpu_va;
}
struct nvgpu_mem *nvgpu_pmu_pg_buf(struct nvgpu_pmu *pmu)
{
return &pmu->pg->pg_buf;
}
void *nvgpu_pmu_pg_buf_get_cpu_va(struct nvgpu_pmu *pmu)
{
return pmu->pg->pg_buf.cpu_va;
}

4
drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h
View File

@@ -141,4 +141,8 @@ int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries); void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id); bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id);
u64 nvgpu_pmu_pg_buf_get_gpu_va(struct nvgpu_pmu *pmu);
struct nvgpu_mem *nvgpu_pmu_pg_buf(struct nvgpu_pmu *pmu);
void *nvgpu_pmu_pg_buf_get_cpu_va(struct nvgpu_pmu *pmu);
#endif /* NVGPU_PMU_PG_H */ #endif /* NVGPU_PMU_PG_H */