nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: unit: branch coverage for gp10b engine HAL

Browse Source 
Add remaining branch coverage for:
- gp10b_engine_init_ce_info (invalid enum read from dev info).

Jira NVGPU-4673

Change-Id: Ibeb673374f547d18a9897eb9dedc7502345461b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265793
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-12-17 13:44:09 -05:00
committed by Alex Waterman
parent 8ea850ccb6
commit a5470fab90
1 changed files with 20 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
userspace/units/fifo/engine/gp10b/nvgpu-engine-gp10b.c
View File

@@ -81,7 +81,8 @@ static inline void subtest_setup(struct unit_module *m, u32 branches)
#define F_ENGINE_INIT_CE_INFO_GRCE BIT(5) #define F_ENGINE_INIT_CE_INFO_GRCE BIT(5)
#define F_ENGINE_INIT_CE_INFO_FAULT_ID_0 BIT(6) #define F_ENGINE_INIT_CE_INFO_FAULT_ID_0 BIT(6)
#define F_ENGINE_INIT_CE_INFO_GET_INST_NULL BIT(7) #define F_ENGINE_INIT_CE_INFO_GET_INST_NULL BIT(7)
#define F_ENGINE_INIT_CE_INFO_LAST BIT(8) #define F_ENGINE_INIT_CE_INFO_INVAL_ENUM BIT(8)
#define F_ENGINE_INIT_CE_INFO_LAST BIT(9)
static u32 wrap_top_get_num_engine_type_entries(struct gk20a *g, static u32 wrap_top_get_num_engine_type_entries(struct gk20a *g,
u32 engine_type) u32 engine_type)
@@ -137,6 +138,13 @@ static int wrap_top_get_device_info(struct gk20a *g,
return 0; return 0;
} }
if (branches & F_ENGINE_INIT_CE_INFO_INVAL_ENUM) {
dev_info->runlist_id = 1;
dev_info->engine_id = 1;
dev_info->engine_type = 5;
return 0;
}
done: done:
return u.gops.top.get_device_info(g, dev_info, engine_type, inst_id); return u.gops.top.get_device_info(g, dev_info, engine_type, inst_id);
@@ -178,11 +186,13 @@ int test_gp10b_engine_init_ce_info(struct unit_module *m,
"grce", "grce",
"fault_id_0", "fault_id_0",
"get_inst_null", "get_inst_null",
"inval_enum"
}; };
u32 prune = u32 prune =
F_ENGINE_INIT_CE_INFO_GET_NUM_ENGINES_NULL | F_ENGINE_INIT_CE_INFO_GET_NUM_ENGINES_NULL |
F_ENGINE_INIT_CE_INFO_NO_LCE | fail; F_ENGINE_INIT_CE_INFO_NO_LCE |
u32 branches; F_ENGINE_INIT_CE_INFO_INVAL_ENUM | fail;
u32 branches = 0;
u32 num_lce; u32 num_lce;
u.m = m; u.m = m;
@@ -219,7 +229,8 @@ int test_gp10b_engine_init_ce_info(struct unit_module *m,
err = gp10b_engine_init_ce_info(f); err = gp10b_engine_init_ce_info(f);
if ((branches & F_ENGINE_INIT_CE_INFO_GET_NUM_ENGINES_NULL) || if ((branches & F_ENGINE_INIT_CE_INFO_GET_NUM_ENGINES_NULL) ||
(branches & F_ENGINE_INIT_CE_INFO_NO_LCE)) { (branches & F_ENGINE_INIT_CE_INFO_NO_LCE) ||
(branches & F_ENGINE_INIT_CE_INFO_INVAL_ENUM)) {
num_lce = 0; num_lce = 0;
} else { } else {
num_lce = g->ops.top.get_num_engine_type_entries(g, NVGPU_ENGINE_LCE); num_lce = g->ops.top.get_num_engine_type_entries(g, NVGPU_ENGINE_LCE);
@@ -236,6 +247,11 @@ int test_gp10b_engine_init_ce_info(struct unit_module *m,
ret = UNIT_SUCCESS; ret = UNIT_SUCCESS;
done: done:
if (ret != UNIT_SUCCESS) {
unit_err(m, "%s branches=%s\n", __func__,
branches_str(branches, labels));
}
g->ops = u.gops; g->ops = u.gops;
return ret; return ret;
} }