diff --git a/drivers/gpu/nvgpu/common/ce/ce.c b/drivers/gpu/nvgpu/common/ce/ce.c
index 2b149f3d5..858a833b9 100644
--- a/drivers/gpu/nvgpu/common/ce/ce.c
+++ b/drivers/gpu/nvgpu/common/ce/ce.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -46,6 +46,10 @@ int nvgpu_ce_init_support(struct gk20a *g)
 
 	nvgpu_cg_blcg_ce_load_enable(g);
 
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
+	nvgpu_cg_elcg_ce_load_enable(g);
+#endif
+
 	if (g->ops.ce.init_prod_values != NULL) {
 		g->ops.ce.init_prod_values(g);
 	}
diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c
index ba366734b..543957e5f 100644
--- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c
+++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c
@@ -490,6 +490,11 @@ void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable)
 			nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
 		}
 	}
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
+	if (g->ops.cg.elcg_ce_load_gating_prod != NULL) {
+		g->ops.cg.elcg_ce_load_gating_prod(g, g->elcg_enabled);
+	}
+#endif
 	nvgpu_mutex_release(&g->cg_pg_lock);
 }
 
@@ -623,4 +628,21 @@ void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
 done:
 	nvgpu_mutex_release(&g->cg_pg_lock);
 }
+
+void nvgpu_cg_elcg_ce_load_enable(struct gk20a *g)
+{
+	nvgpu_log_fn(g, " ");
+
+	nvgpu_mutex_acquire(&g->cg_pg_lock);
+	if (!g->elcg_enabled) {
+		goto done;
+	}
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
+	if (g->ops.cg.elcg_ce_load_gating_prod != NULL) {
+		g->ops.cg.elcg_ce_load_gating_prod(g, true);
+	}
+#endif
+done:
+	nvgpu_mutex_release(&g->cg_pg_lock);
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h
index f333d00b8..41ddc4636 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h
@@ -447,6 +447,25 @@ void nvgpu_cg_slcg_therm_load_enable(struct gk20a *g);
  */
 void nvgpu_cg_slcg_ce2_load_enable(struct gk20a *g);
 
+/**
+ * @brief During nvgpu power-on, as part of CE initialization,
+ *        this function is called to load register configuration
+ *        for ELCG for CE.
+ *
+ * @param g [in] The GPU driver struct.
+ *
+ * Checks the platform software capability elcg_enabled and programs registers
+ * for configuring production gating values for ELCG for CE. This is called
+ * in #nvgpu_ce_init_support.
+ *
+ * Steps:
+ * - Acquire the mutex #cg_pg_lock.
+ * - Check if #elcg_enabled is set, else skip ELCG programming.
+ * - Load ELCG prod settings for CE.
+ * - Release the mutex #cg_pg_lock.
+ */
+void nvgpu_cg_elcg_ce_load_enable(struct gk20a *g);
+
 #ifdef CONFIG_NVGPU_NON_FUSA
 
 void nvgpu_cg_elcg_enable(struct gk20a *g);