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gpu: nvgpu: RPC interface support
- Created nv_pmu_rpc_cmd & nv_pmu_rpc_msg struct, & added member rpc under pmu_cmd & pmu_msg - Created RPC header interface - Created RPC desc struct & added as member to pmu payload - Defined PMU_RPC_EXECUTE() to convert different RPC request to make generic RPC call. - nvgpu_pmu_rpc_execute() function to execute RPC request by creating required RPC payload & send request to PMU to execute. - nvgpu_pmu_rpc_execute() function as default callback handler for RPC if caller not provided callback - Modified nvgpu_pmu_rpc_execute() function to include check of RPC payload parameter. - Modified nvgpu_pmu_cmd_post() function to handle RPC payload request. JIRA GPUT19X-137 Change-Id: Iac140eb6b98d6bae06a089e71c96f15068fe7e7b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1613266 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
committed by
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parent
badfffe3ef
commit
a57258e9b1
@@ -410,11 +410,13 @@ static bool pmu_validate_cmd(struct nvgpu_pmu *pmu, struct pmu_cmd *cmd,
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if (payload == NULL)
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return true;
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if (payload->in.buf == NULL && payload->out.buf == NULL)
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if (payload->in.buf == NULL && payload->out.buf == NULL &&
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payload->rpc.prpc == NULL)
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goto invalid_cmd;
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if ((payload->in.buf != NULL && payload->in.size == 0) ||
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(payload->out.buf != NULL && payload->out.size == 0))
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(payload->out.buf != NULL && payload->out.size == 0) ||
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(payload->rpc.prpc != NULL && payload->rpc.size_rpc == 0))
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goto invalid_cmd;
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in_size = PMU_CMD_HDR_SIZE;
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@@ -491,55 +493,61 @@ clean_up:
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return err;
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}
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int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
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struct pmu_msg *msg, struct pmu_payload *payload,
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u32 queue_id, pmu_callback callback, void *cb_param,
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u32 *seq_desc, unsigned long timeout)
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static int pmu_cmd_payload_extract_rpc(struct gk20a *g, struct pmu_cmd *cmd,
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struct pmu_payload *payload, struct pmu_sequence *seq)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct pmu_v *pv = &g->ops.pmu_ver;
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struct pmu_sequence *seq;
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void *in = NULL, *out = NULL;
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int err;
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u16 dmem_alloc_size = 0;
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u32 dmem_alloc_offset = 0;
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int err = 0;
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nvgpu_log_fn(g, " ");
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if ((!cmd) || (!seq_desc) || (!pmu->pmu_ready)) {
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if (!cmd)
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nvgpu_warn(g, "%s(): PMU cmd buffer is NULL", __func__);
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else if (!seq_desc)
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nvgpu_warn(g, "%s(): Seq descriptor is NULL", __func__);
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else
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nvgpu_warn(g, "%s(): PMU is not ready", __func__);
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WARN_ON(1);
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return -EINVAL;
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dmem_alloc_size = payload->rpc.size_rpc +
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payload->rpc.size_scratch;
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dmem_alloc_offset = nvgpu_alloc(&pmu->dmem, dmem_alloc_size);
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if (!dmem_alloc_offset) {
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err = -ENOMEM;
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goto clean_up;
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}
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if (!pmu_validate_cmd(pmu, cmd, msg, payload, queue_id))
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return -EINVAL;
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nvgpu_flcn_copy_to_dmem(pmu->flcn, dmem_alloc_offset,
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payload->rpc.prpc, payload->rpc.size_rpc, 0);
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err = pmu_seq_acquire(pmu, &seq);
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cmd->cmd.rpc.rpc_dmem_size = payload->rpc.size_rpc;
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cmd->cmd.rpc.rpc_dmem_ptr = dmem_alloc_offset;
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seq->out_payload = payload->rpc.prpc;
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pv->pmu_allocation_set_dmem_size(pmu,
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pv->get_pmu_seq_out_a_ptr(seq),
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payload->rpc.size_rpc);
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pv->pmu_allocation_set_dmem_offset(pmu,
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pv->get_pmu_seq_out_a_ptr(seq),
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dmem_alloc_offset);
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clean_up:
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if (err)
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return err;
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nvgpu_log_fn(g, "fail");
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else
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nvgpu_log_fn(g, "done");
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cmd->hdr.seq_id = seq->id;
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return err;
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}
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cmd->hdr.ctrl_flags = 0;
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cmd->hdr.ctrl_flags |= PMU_CMD_FLAGS_STATUS;
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cmd->hdr.ctrl_flags |= PMU_CMD_FLAGS_INTR;
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static int pmu_cmd_payload_extract(struct gk20a *g, struct pmu_cmd *cmd,
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struct pmu_payload *payload, struct pmu_sequence *seq)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct pmu_v *pv = &g->ops.pmu_ver;
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void *in = NULL, *out = NULL;
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int err = 0;
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seq->callback = callback;
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seq->cb_params = cb_param;
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seq->msg = msg;
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seq->out_payload = NULL;
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seq->desc = pmu->next_seq_desc++;
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nvgpu_log_fn(g, " ");
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if (payload)
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seq->out_payload = payload->out.buf;
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*seq_desc = seq->desc;
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if (payload && payload->in.offset != 0) {
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pv->set_pmu_allocation_ptr(pmu, &in,
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((u8 *)&cmd->cmd + payload->in.offset));
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@@ -553,7 +561,7 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
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*(pv->pmu_allocation_get_dmem_offset_addr(pmu, in)) =
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nvgpu_alloc(&pmu->dmem,
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pv->pmu_allocation_get_dmem_size(pmu, in));
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pv->pmu_allocation_get_dmem_size(pmu, in));
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if (!*(pv->pmu_allocation_get_dmem_offset_addr(pmu, in)))
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goto clean_up;
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@@ -596,7 +604,8 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
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if (payload->in.buf != payload->out.buf) {
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*(pv->pmu_allocation_get_dmem_offset_addr(pmu, out)) =
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nvgpu_alloc(&pmu->dmem,
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pv->pmu_allocation_get_dmem_size(pmu, out));
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pv->pmu_allocation_get_dmem_size(pmu,
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out));
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if (!*(pv->pmu_allocation_get_dmem_offset_addr(pmu,
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out)))
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goto clean_up;
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@@ -630,7 +639,72 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
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}
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clean_up:
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if (err) {
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nvgpu_log_fn(g, "fail");
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if (in)
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nvgpu_free(&pmu->dmem,
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pv->pmu_allocation_get_dmem_offset(pmu, in));
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if (out)
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nvgpu_free(&pmu->dmem,
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pv->pmu_allocation_get_dmem_offset(pmu, out));
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} else
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nvgpu_log_fn(g, "done");
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return err;
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}
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int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
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struct pmu_msg *msg, struct pmu_payload *payload,
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u32 queue_id, pmu_callback callback, void *cb_param,
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u32 *seq_desc, unsigned long timeout)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct pmu_sequence *seq;
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int err;
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nvgpu_log_fn(g, " ");
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if ((!cmd) || (!seq_desc) || (!pmu->pmu_ready)) {
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if (!cmd)
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nvgpu_warn(g, "%s(): PMU cmd buffer is NULL", __func__);
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else if (!seq_desc)
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nvgpu_warn(g, "%s(): Seq descriptor is NULL", __func__);
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else
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nvgpu_warn(g, "%s(): PMU is not ready", __func__);
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WARN_ON(1);
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return -EINVAL;
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}
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if (!pmu_validate_cmd(pmu, cmd, msg, payload, queue_id))
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return -EINVAL;
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err = pmu_seq_acquire(pmu, &seq);
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if (err)
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return err;
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cmd->hdr.seq_id = seq->id;
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cmd->hdr.ctrl_flags = 0;
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cmd->hdr.ctrl_flags |= PMU_CMD_FLAGS_STATUS;
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cmd->hdr.ctrl_flags |= PMU_CMD_FLAGS_INTR;
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seq->callback = callback;
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seq->cb_params = cb_param;
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seq->msg = msg;
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seq->out_payload = NULL;
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seq->desc = pmu->next_seq_desc++;
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*seq_desc = seq->desc;
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if (cmd->cmd.rpc.cmd_type == NV_PMU_RPC_CMD_ID)
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err = pmu_cmd_payload_extract_rpc(g, cmd, payload, seq);
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else
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err = pmu_cmd_payload_extract(g, cmd, payload, seq);
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if (err)
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goto clean_up;
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seq->state = PMU_SEQ_STATE_USED;
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@@ -644,12 +718,6 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
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clean_up:
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nvgpu_log_fn(g, "fail");
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if (in)
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nvgpu_free(&pmu->dmem,
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pv->pmu_allocation_get_dmem_offset(pmu, in));
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if (out)
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nvgpu_free(&pmu->dmem,
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pv->pmu_allocation_get_dmem_offset(pmu, out));
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pmu_seq_release(pmu, seq);
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return err;
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@@ -666,6 +734,7 @@ static int pmu_response_handle(struct nvgpu_pmu *pmu,
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nvgpu_log_fn(g, " ");
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seq = &pmu->seq[msg->hdr.seq_id];
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if (seq->state != PMU_SEQ_STATE_USED &&
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seq->state != PMU_SEQ_STATE_CANCELLED) {
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nvgpu_err(g, "msg for an unknown sequence %d", seq->id);
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@@ -905,3 +974,88 @@ int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
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return -ETIMEDOUT;
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}
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static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg,
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void *param, u32 handle, u32 status)
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{
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struct nv_pmu_rpc_header rpc;
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memset(&rpc, 0, sizeof(struct nv_pmu_rpc_header));
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if (param)
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memcpy(&rpc, param, sizeof(struct nv_pmu_rpc_header));
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if (rpc.flcn_status) {
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nvgpu_err(g, " failed RPC response, status=0x%x, func=0x%x",
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rpc.flcn_status, rpc.function);
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goto exit;
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}
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switch (msg->hdr.unit_id) {
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/* TBD case will be added */
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default:
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nvgpu_err(g, " Invalid RPC response, stats 0x%x",
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rpc.flcn_status);
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break;
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}
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exit:
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/* free allocated memory */
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if (param)
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nvgpu_kfree(g, param);
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}
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int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc,
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u16 size_rpc, u16 size_scratch, pmu_callback caller_cb,
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void *caller_cb_param)
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{
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struct gk20a *g = pmu->g;
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struct pmu_cmd cmd;
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struct pmu_payload payload;
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pmu_callback callback = caller_cb;
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void *rpc_buff = NULL;
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void *cb_param = caller_cb_param;
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u32 seq = 0;
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int status = 0;
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if (!pmu->pmu_ready) {
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nvgpu_warn(g, "PMU is not ready to process RPC");
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return -EINVAL;
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}
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rpc_buff = nvgpu_kzalloc(g, size_rpc);
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if (!rpc_buff)
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return -ENOMEM;
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memset(&cmd, 0, sizeof(struct pmu_cmd));
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memset(&payload, 0, sizeof(struct pmu_payload));
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cmd.hdr.unit_id = rpc->unit_id;
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cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct nv_pmu_rpc_cmd);
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cmd.cmd.rpc.cmd_type = NV_PMU_RPC_CMD_ID;
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cmd.cmd.rpc.flags = rpc->flags;
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memcpy(rpc_buff, rpc, size_rpc);
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payload.rpc.prpc = rpc_buff;
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payload.rpc.size_rpc = size_rpc;
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payload.rpc.size_scratch = size_scratch;
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/* assign default RPC handler & buffer */
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if (!callback && !cb_param) {
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callback = pmu_rpc_handler;
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cb_param = rpc_buff;
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}
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status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
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PMU_COMMAND_QUEUE_LPQ, pmu_rpc_handler,
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cb_param, &seq, ~0);
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if (status) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x, func=0x%x",
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status, rpc->function);
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}
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/* if caller passed buff then free allocated RPC buffer */
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if (caller_cb_param)
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nvgpu_kfree(g, rpc_buff);
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return status;
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}
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