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gpu: nvgpu: add support for disabling l3 via DT

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On volta the GPU determines whether to do L3 allocation for a mapping by
checking bit 36 of the physical address. So if a mapping should allocate
lines in the L3 this bit must be set.

However, when the physical addresses for 64GB of RAM uses the 36th bit
resulting in a conflict. Thus, add support for disabling l3 support
for SKUs having 64GB of physical memory.

Bug 3486025
Bug 3469094

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Ic540e754274cf1d9e6625493962699d21509e540
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2661548
(cherry picked from commit 5c0dc7e39d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2676296
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Debarshi Dutta
2022-01-31 08:13:19 +05:30
committed by mobile promotions
parent 856c1c82de
commit a58e8f1867
3 changed files with 15 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/include/nvgpu/enabled.h
View File

@@ -90,6 +90,8 @@ struct gk20a;
"Use physical scatter tables instead of IOMMU"), \ "Use physical scatter tables instead of IOMMU"), \
DEFINE_FLAG(NVGPU_MM_BYPASSES_IOMMU, \ DEFINE_FLAG(NVGPU_MM_BYPASSES_IOMMU, \
"Some chips (using nvlink) bypass the IOMMU on tegra"), \ "Some chips (using nvlink) bypass the IOMMU on tegra"), \
DEFINE_FLAG(NVGPU_DISABLE_L3_SUPPORT, \
"Disable L3 alloc Bit of the physical address"), \
/* Host Flags */ \ /* Host Flags */ \
DEFINE_FLAG(NVGPU_HAS_SYNCPOINTS, "GPU has syncpoints"), \ DEFINE_FLAG(NVGPU_HAS_SYNCPOINTS, "GPU has syncpoints"), \
DEFINE_FLAG(NVGPU_SUPPORT_SYNC_FENCE_FDS, \ DEFINE_FLAG(NVGPU_SUPPORT_SYNC_FENCE_FDS, \

9
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -20,6 +20,7 @@
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/of_platform.h>
#include <uapi/linux/nvgpu.h> #include <uapi/linux/nvgpu.h>
#include <nvgpu/defaults.h> #include <nvgpu/defaults.h>
@@ -317,6 +318,8 @@ int nvgpu_probe(struct gk20a *g,
struct gk20a_platform *platform = dev_get_drvdata(dev); struct gk20a_platform *platform = dev_get_drvdata(dev);
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
int err = 0; int err = 0;
struct device_node *np = dev->of_node;
bool disable_l3_alloc = false;
err = nvgpu_cic_rm_setup(g); err = nvgpu_cic_rm_setup(g);
if (err != 0) { if (err != 0) {
@@ -354,6 +357,12 @@ int nvgpu_probe(struct gk20a *g,
return err; return err;
} }
disable_l3_alloc = of_property_read_bool(np, "disable_l3_alloc");
if (disable_l3_alloc) {
nvgpu_log_info(g, "L3 alloc is disabled");
nvgpu_set_enabled(g, NVGPU_DISABLE_L3_SUPPORT, true);
}
nvgpu_init_mm_vars(g); nvgpu_init_mm_vars(g);
err = gk20a_power_node_init(dev); err = gk20a_power_node_init(dev);
if (err) { if (err) {

2
drivers/gpu/nvgpu/os/linux/vm.c
View File

@@ -56,8 +56,10 @@ static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
core_flags |= NVGPU_VM_MAP_IO_COHERENT; core_flags |= NVGPU_VM_MAP_IO_COHERENT;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE) if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE)
core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE; core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) {
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC) if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC)
core_flags |= NVGPU_VM_MAP_L3_ALLOC; core_flags |= NVGPU_VM_MAP_L3_ALLOC;
}
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL) if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL; core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC) if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)