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gpu: nvgpu: add new gr/config unit to initialize GR configuration

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Add new unit gr/config to initialize GR configuration like GPC/TPC
count, MAX count and mask

Create new structure nvgpu_gr_config that stores all the configuration
and that is owned by the new unit

Move below fields from struct gr_gk20a to nvgpu_gr_config in gr/config.h
Struct gr_gk20a now only holds the pointer to struct nvgpu_gr_config

u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;

u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;

u32 pe_count_per_gpc;

u32 *gpc_tpc_count;
u32 *gpc_ppc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];

u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;

u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;

Remove gr->sys_count since it was already no longer used

common/gr/config/gr_config.c unit now exposes the APIs to initialize
the configuration and also to query the configuration values

nvgpu_gr_config_init() is called to initialize GR configuration from
gr_gk20a_init_gr_config() and gr_gk20a_init_map_tiles() is simply
renamed as nvgpu_gr_config_init_map_tiles()

Expose new API nvgpu_gr_config_deinit() to deinit the configuration

Expose nvgpu_gr_config_get_*() APIs to query above configuration
fields stored in nvgpu_gr_config structure

Update vgpu_gr_init_gr_config() to initialize the configuration
from gr->config structure

Chip specific HALs that access GR register for initialization
are implemented in common/gr/config/gr_config_gm20b.c
Set these HALs for all GPUs

Jira NVGPU-1879

Change-Id: Ided658b43124ea61b9f273b82b73fdde4ed3c8f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012167
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-01-30 19:22:39 +05:30
committed by mobile promotions
parent e212e851a3
commit a5eb150635
32 changed files with 1401 additions and 863 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -32,6 +32,7 @@
#include <nvgpu/list.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/channel.h>
#include <nvgpu/pmu/pmgr.h>
@@ -281,10 +282,10 @@ gk20a_ctrl_ioctl_gpu_characteristics(
gpu.L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g);
gpu.on_board_video_memory_size = 0; /* integrated GPU */
gpu.num_gpc = g->gr.gpc_count;
gpu.max_gpc_count = g->gr.max_gpc_count;
gpu.num_gpc = nvgpu_gr_config_get_gpc_count(g->gr.config);
gpu.max_gpc_count = nvgpu_gr_config_get_max_gpc_count(g->gr.config);
gpu.num_tpc_per_gpc = g->gr.max_tpc_per_gpc_count;
gpu.num_tpc_per_gpc = nvgpu_gr_config_get_max_tpc_per_gpc_count(g->gr.config);
gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */
@@ -293,7 +294,7 @@ gk20a_ctrl_ioctl_gpu_characteristics(
if (g->ops.gr.get_gpc_mask) {
gpu.gpc_mask = g->ops.gr.get_gpc_mask(g);
} else {
gpu.gpc_mask = BIT32(g->gr.gpc_count) - 1;
gpu.gpc_mask = BIT32(gpu.num_gpc) - 1;
}
gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g);
@@ -553,7 +554,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
{
struct gr_gk20a *gr = &g->gr;
int err = 0;
const u32 gpc_tpc_mask_size = sizeof(u32) * gr->max_gpc_count;
const u32 gpc_tpc_mask_size = sizeof(u32) * gr->config->max_gpc_count;
if (args->mask_buf_size > 0) {
size_t write_size = gpc_tpc_mask_size;
@@ -564,7 +565,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
err = copy_to_user((void __user *)(uintptr_t)
args->mask_buf_addr,
gr->gpc_tpc_mask, write_size);
gr->config->gpc_tpc_mask, write_size);
}
if (err == 0)
@@ -687,7 +688,8 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
struct nvgpu_warpstate *w_state = NULL;
u32 sm_count, ioctl_size, size, sm_id;
sm_count = g->gr.gpc_count * g->gr.tpc_count;
sm_count = nvgpu_gr_config_get_gpc_count(g->gr.config) *
nvgpu_gr_config_get_tpc_count(g->gr.config);
ioctl_size = sm_count * sizeof(struct warpstate);
ioctl_w_state = nvgpu_kzalloc(g, ioctl_size);