From a5ecf0da7c77434d28006d3e7cbfd1db39b8c37f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 22 Jun 2020 14:35:27 -0700 Subject: [PATCH] gpu: nvgpu: add info prints for sw_ctx_load and sw_non_ctx_load This will help debug issues where registers are incorrectly updated by ctxsw ucode or are overwritten after nvgpu init sequence sets the value. Bug 3029888 Change-Id: I510763a767145500715fb260799b0dd98e59778f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2365212 Reviewed-by: automaticguardword Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 2 ++ drivers/gpu/nvgpu/common/gr/obj_ctx.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 84b1851dd..ab2ff2b1b 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -573,6 +573,7 @@ static int gr_init_reset_enable_hw(struct gk20a *g) enable_gr_interrupts(g); /* load non_ctx init */ + nvgpu_log_info(g, "begin: netlist: sw_non_ctx_load: register writes"); for (i = 0; i < sw_non_ctx_load->count; i++) { nvgpu_writel(g, sw_non_ctx_load->l[i].addr, sw_non_ctx_load->l[i].value); @@ -582,6 +583,7 @@ static int gr_init_reset_enable_hw(struct gk20a *g) nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(g); nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(g); #endif + nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes"); err = g->ops.gr.falcon.wait_mem_scrubbing(g); if (err != 0) { diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index 055180a1f..b6e842691 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -467,10 +467,12 @@ static int nvgpu_gr_obj_ctx_init_hw_state(struct gk20a *g, err = g->ops.gr.init.wait_idle(g); /* load ctx init */ + nvgpu_log_info(g, "begin: netlist: sw_ctx_load: register writes"); for (i = 0U; i < sw_ctx_load->count; i++) { nvgpu_writel(g, sw_ctx_load->l[i].addr, sw_ctx_load->l[i].value); } + nvgpu_log_info(g, "end: netlist: sw_ctx_load: register writes"); #ifdef CONFIG_NVGPU_GRAPHICS if (g->ops.gr.init.preemption_state != NULL) {