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gpu: nvgpu: gv100: enable syncpt shim for nvlink
Get host1x node reference from c1_rp device tree node, and enable syncpoints shim in case of nvlink. JIRA EVLR-2441 JIRA EVLR-2585 Change-Id: Idbf1edf656557f2ed2d3bd27393c2f4d5d1ad75a Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1663360 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -258,4 +258,37 @@ u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
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{
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{
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return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
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return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id);
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}
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}
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int nvgpu_nvhost_syncpt_init(struct gk20a *g)
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{
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int err = 0;
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if (!g->has_syncpoints)
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return -ENOSYS;
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err = nvgpu_get_nvhost_dev(g);
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if (err) {
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nvgpu_err(g, "host1x device not available");
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g->has_syncpoints = false;
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return -ENOSYS;
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}
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err = nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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g->nvhost_dev,
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&g->syncpt_unit_base,
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&g->syncpt_unit_size);
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if (err) {
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nvgpu_err(g, "Failed to get syncpt interface");
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g->has_syncpoints = false;
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return -ENOSYS;
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}
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g->syncpt_size =
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nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(1);
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nvgpu_info(g, "syncpt_unit_base %llx syncpt_unit_size %zx size %x\n",
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g->syncpt_unit_base, g->syncpt_unit_size,
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g->syncpt_size);
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return 0;
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}
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#endif
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#endif
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@@ -20,6 +20,7 @@
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#include <linux/of_platform.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <nvgpu/nvhost.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/enabled.h>
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@@ -316,6 +317,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.vbios_min_version = 0x88000126,
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.vbios_min_version = 0x88000126,
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.hardcode_sw_threshold = false,
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.hardcode_sw_threshold = false,
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.run_preos = true,
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.run_preos = true,
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.has_syncpoints = true,
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},
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},
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{ /* SKU250 */
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{ /* SKU250 */
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/* ptimer src frequency in hz */
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/* ptimer src frequency in hz */
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@@ -350,6 +352,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.vbios_min_version = 0x1,
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.vbios_min_version = 0x1,
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.hardcode_sw_threshold = false,
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.hardcode_sw_threshold = false,
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.run_preos = true,
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.run_preos = true,
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.has_syncpoints = true,
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},
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},
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{ /* SKU 0x1e3f */
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{ /* SKU 0x1e3f */
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/* ptimer src frequency in hz */
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/* ptimer src frequency in hz */
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@@ -700,6 +703,17 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
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nvgpu_err(g, "fatal error probing nvlink, bailing out");
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nvgpu_err(g, "fatal error probing nvlink, bailing out");
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goto err_free_irq;
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goto err_free_irq;
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}
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}
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/* Enable Semaphore SHIM on nvlink only for now. */
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
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g->has_syncpoints = false;
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} else {
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err = nvgpu_nvhost_syncpt_init(g);
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if (err) {
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if (err != -ENOSYS) {
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nvgpu_err(g, "syncpt init failed");
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goto err_free_irq;
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}
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}
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}
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}
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g->mm.has_physical_mode = false;
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g->mm.has_physical_mode = false;
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@@ -49,38 +49,14 @@ static void gr_gv11b_remove_sysfs(struct device *dev);
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static int gv11b_tegra_probe(struct device *dev)
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static int gv11b_tegra_probe(struct device *dev)
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{
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{
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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struct gk20a_platform *platform = dev_get_drvdata(dev);
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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int err;
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struct gk20a *g = platform->g;
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int err = 0;
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if (g->has_syncpoints) {
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err = nvgpu_nvhost_syncpt_init(platform->g);
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err = nvgpu_get_nvhost_dev(g);
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if (err) {
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if (err) {
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if (err != -ENOSYS)
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dev_err(dev, "host1x device not available");
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return err;
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return err;
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}
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}
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}
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if (g->has_syncpoints) {
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err = nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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g->nvhost_dev,
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&g->syncpt_unit_base,
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&g->syncpt_unit_size);
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if (err) {
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dev_err(dev, "Failed to get syncpt interface");
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return -ENOSYS;
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}
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g->syncpt_size =
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nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(1);
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nvgpu_info(g, "syncpt_unit_base %llx "
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"syncpt_unit_size %zx size %x\n",
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g->syncpt_unit_base, g->syncpt_unit_size,
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g->syncpt_size);
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}
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#else
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g->has_syncpoints = false;
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#endif
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err = gk20a_tegra_init_secure_alloc(platform);
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err = gk20a_tegra_init_secure_alloc(platform);
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if (err)
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if (err)
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return err;
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return err;
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@@ -182,15 +182,11 @@ int gk20a_finalize_poweron(struct gk20a *g)
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}
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}
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if (nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) {
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if (nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) {
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if (g->ops.nvlink.init) {
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err = g->ops.nvlink.init(g);
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err = g->ops.nvlink.init(g);
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if (err) {
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if (err) {
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nvgpu_err(g, "failed to init nvlink");
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nvgpu_err(g, "failed to init nvlink");
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goto done;
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK,
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}
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false);
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}
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} else
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
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}
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}
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if (g->ops.fb.mem_unlock) {
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if (g->ops.fb.mem_unlock) {
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@@ -248,6 +248,10 @@ int gv100_init_gpu_characteristics(struct gk20a *g)
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
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if (g->has_syncpoints) {
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
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}
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return 0;
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return 0;
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}
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}
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@@ -1636,8 +1636,10 @@ int gv100_nvlink_init(struct gk20a *g)
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return -ENODEV;
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return -ENODEV;
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err = nvgpu_nvlink_enumerate(g);
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err = nvgpu_nvlink_enumerate(g);
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if (err)
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if (err) {
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return err;
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nvgpu_err(g, "failed to enumerate nvlink");
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goto fail;
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}
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/* Set HSHUB and SG_PHY */
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/* Set HSHUB and SG_PHY */
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__nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, true);
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__nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, true);
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@@ -1645,10 +1647,15 @@ int gv100_nvlink_init(struct gk20a *g)
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err = g->ops.fb.enable_nvlink(g);
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err = g->ops.fb.enable_nvlink(g);
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if (err) {
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if (err) {
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nvgpu_err(g, "failed switch to nvlink sysmem");
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nvgpu_err(g, "failed switch to nvlink sysmem");
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return err;
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goto fail;
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}
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}
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return err;
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return err;
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fail:
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__nvgpu_set_enabled(g, NVGPU_MM_USE_PHYSICAL_SG, false);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
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return err;
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}
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}
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/*
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/*
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@@ -89,11 +89,20 @@ int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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struct nvgpu_nvhost_dev *nvhost_dev,
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struct nvgpu_nvhost_dev *nvhost_dev,
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u64 *base, size_t *size);
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u64 *base, size_t *size);
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u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id);
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u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id);
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int nvgpu_nvhost_syncpt_init(struct gk20a *g);
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#else
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#else
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static inline int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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static inline int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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struct nvgpu_nvhost_dev *nvhost_dev,
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struct nvgpu_nvhost_dev *nvhost_dev,
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u64 *base, size_t *size) { return -EINVAL; }
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u64 *base, size_t *size)
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static inline u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) {
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{
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return -EINVAL;
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}
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static inline u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
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{
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return 0;
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}
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static inline int nvgpu_nvhost_syncpt_init(struct gk20a *g)
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{
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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